Lines Matching +full:1 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
52 {0, 1},
53 {1, 2},
61 {1, 4},
67 {1, 4},
88 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
90 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
91 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
92 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
95 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
96 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
97 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
105 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
114 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
120 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
134 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
143 BUS_MSTOP(1, BIT(0))),
145 BUS_MSTOP(1, BIT(0))),
150 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
156 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
158 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
159 BUS_MSTOP(1, BIT(1))),
160 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
161 BUS_MSTOP(1, BIT(2))),
162 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
163 BUS_MSTOP(1, BIT(3))),
164 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
165 BUS_MSTOP(1, BIT(4))),
166 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
167 BUS_MSTOP(1, BIT(5))),
168 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
169 BUS_MSTOP(1, BIT(6))),
170 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
171 BUS_MSTOP(1, BIT(7))),
172 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
173 BUS_MSTOP(1, BIT(8))),
186 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
199 BUS_MSTOP(9, BIT(4))),
201 BUS_MSTOP(9, BIT(4))),
203 BUS_MSTOP(9, BIT(4))),
205 BUS_MSTOP(9, BIT(5))),
207 BUS_MSTOP(9, BIT(5))),
209 BUS_MSTOP(9, BIT(5))),
211 BUS_MSTOP(9, BIT(6))),
212 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
213 BUS_MSTOP(9, BIT(6))),
215 BUS_MSTOP(9, BIT(6))),
217 BUS_MSTOP(9, BIT(7))),
219 BUS_MSTOP(9, BIT(7))),
221 BUS_MSTOP(9, BIT(7))),
225 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
226 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
227 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
228 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
232 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
233 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
240 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
242 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
243 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
244 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
245 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
246 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
247 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
248 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
249 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
253 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
258 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
265 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */