Lines Matching +full:1 +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
52 {0, 1},
53 {1, 2},
61 {1, 4},
67 {1, 4},
88 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
90 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
91 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
92 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
95 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
96 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
97 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
105 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
114 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
118 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
120 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
121 BUS_MSTOP(3, BIT(5))),
123 BUS_MSTOP(5, BIT(10))),
125 BUS_MSTOP(5, BIT(11))),
126 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
143 BUS_MSTOP(1, BIT(0))),
145 BUS_MSTOP(1, BIT(0))),
147 BUS_MSTOP(5, BIT(12))),
148 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
149 BUS_MSTOP(5, BIT(12))),
150 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
151 BUS_MSTOP(5, BIT(13))),
152 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
153 BUS_MSTOP(5, BIT(13))),
159 BUS_MSTOP(1, BIT(1))),
160 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
161 BUS_MSTOP(1, BIT(2))),
163 BUS_MSTOP(1, BIT(3))),
165 BUS_MSTOP(1, BIT(4))),
167 BUS_MSTOP(1, BIT(5))),
169 BUS_MSTOP(1, BIT(6))),
171 BUS_MSTOP(1, BIT(7))),
173 BUS_MSTOP(1, BIT(8))),
174 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
176 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
178 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
180 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
182 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
184 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
186 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
188 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
190 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
192 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
194 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
196 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
204 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
205 BUS_MSTOP(9, BIT(5))),
207 BUS_MSTOP(9, BIT(5))),
209 BUS_MSTOP(9, BIT(5))),
225 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
226 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
227 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
228 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
232 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
233 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
236 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
237 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
254 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
255 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
256 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
257 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
258 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
259 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
260 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
261 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
262 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
263 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
265 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */