Lines Matching +full:1 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
43 {0, 1},
44 {1, 2},
52 {1, 4},
72 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
74 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
77 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
80 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
89 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
93 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
97 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
99 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
100 BUS_MSTOP(1, BIT(1))),
101 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
102 BUS_MSTOP(1, BIT(2))),
103 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
104 BUS_MSTOP(1, BIT(3))),
105 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
106 BUS_MSTOP(1, BIT(4))),
107 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
108 BUS_MSTOP(1, BIT(5))),
109 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
110 BUS_MSTOP(1, BIT(6))),
111 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
112 BUS_MSTOP(1, BIT(7))),
113 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
114 BUS_MSTOP(1, BIT(8))),
118 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
119 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
120 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
121 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
122 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
123 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
124 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
125 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
126 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
127 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
128 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
129 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */