1 // SPDX-License-Identifier: GPL-2.0
3  * Mediatek MT7621 Clock Driver
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/mt7621-clk.h>
17 #include <dt-bindings/reset/mt7621-reset.h>
37 	struct regmap *memc;  member
101 	struct regmap *sysc = clk_gate->priv->sysc;  in mt7621_gate_enable()
104 				  clk_gate->bit_idx, clk_gate->bit_idx);  in mt7621_gate_enable()
110 	struct regmap *sysc = clk_gate->priv->sysc;  in mt7621_gate_disable()
112 	regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);  in mt7621_gate_disable()
118 	struct regmap *sysc = clk_gate->priv->sysc;  in mt7621_gate_is_enabled()
124 	return val & clk_gate->bit_idx;  in mt7621_gate_is_enabled()
145 		.parent_names = &sclk->parent_name,  in mt7621_gate_ops_init()
147 		.name = sclk->name,  in mt7621_gate_ops_init()
150 	sclk->hw.init = &init;  in mt7621_gate_ops_init()
151 	return devm_clk_hw_register(dev, &sclk->hw);  in mt7621_gate_ops_init()
158 	struct clk_hw **hws = clk_data->hws;  in mt7621_register_gates()
164 		sclk->priv = priv;  in mt7621_register_gates()
167 			dev_err(dev, "Couldn't register clock %s\n", sclk->name);  in mt7621_register_gates()
171 		hws[sclk->idx] = &sclk->hw;  in mt7621_register_gates()
177 	while (--i >= 0) {  in mt7621_register_gates()
179 		clk_hw_unregister(&sclk->hw);  in mt7621_register_gates()
203 	struct clk_hw **hws = clk_data->hws;  in mt7621_register_fixed_clocks()
209 		sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name,  in mt7621_register_fixed_clocks()
210 						      sclk->parent_name, 0,  in mt7621_register_fixed_clocks()
211 						      sclk->rate);  in mt7621_register_fixed_clocks()
212 		if (IS_ERR(sclk->hw)) {  in mt7621_register_fixed_clocks()
213 			dev_err(dev, "Couldn't register clock %s\n", sclk->name);  in mt7621_register_fixed_clocks()
214 			ret = PTR_ERR(sclk->hw);  in mt7621_register_fixed_clocks()
218 		hws[sclk->idx] = sclk->hw;  in mt7621_register_fixed_clocks()
224 	while (--i >= 0) {  in mt7621_register_fixed_clocks()
226 		clk_hw_unregister_fixed_rate(sclk->hw);  in mt7621_register_fixed_clocks()
240 	struct regmap *sysc = clk->priv->sysc;  in mt7621_xtal_recalc_rate()
259 	struct regmap *sysc = clk->priv->sysc;  in mt7621_cpu_recalc_rate()
260 	struct regmap *memc = clk->priv->memc;  in mt7621_cpu_recalc_rate()  local
277 		regmap_read(memc, MEMC_REG_CPU_PLL, &pll);  in mt7621_cpu_recalc_rate()
321 	struct clk_hw **hws = clk_data->hws;  in mt7621_register_early_clocks()
327 		sclk->priv = priv;  in mt7621_register_early_clocks()
328 		ret = of_clk_hw_register(np, &sclk->hw);  in mt7621_register_early_clocks()
334 		hws[i] = &sclk->hw;  in mt7621_register_early_clocks()
335 		mt7621_clk_early[i] = &sclk->hw;  in mt7621_register_early_clocks()
339 		mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER);  in mt7621_register_early_clocks()
344 	while (--i >= 0) {  in mt7621_register_early_clocks()
346 		clk_hw_unregister(&sclk->hw);  in mt7621_register_early_clocks()
361 	priv->sysc = syscon_node_to_regmap(node);  in mt7621_clk_init()
362 	if (IS_ERR(priv->sysc)) {  in mt7621_clk_init()
367 	priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl");  in mt7621_clk_init()
368 	if (IS_ERR(priv->memc)) {  in mt7621_clk_init()
369 		pr_err("Could not get memc syscon regmap\n");  in mt7621_clk_init()
385 	clk_data->num = count;  in mt7621_clk_init()
399 		clk_hw_unregister(&sclk->hw);  in mt7621_clk_init()
408 CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
424 	struct regmap *sysc = data->sysc;  in mt7621_assert_device()
433 	struct regmap *sysc = data->sysc;  in mt7621_deassert_device()
453 	unsigned long id = reset_spec->args[0];  in mt7621_rst_xlate()
455 	if (id == MT7621_RST_SYS || id >= rcdev->nr_resets)  in mt7621_rst_xlate()
456 		return -EINVAL;  in mt7621_rst_xlate()
473 		return -ENOMEM;  in mt7621_reset_init()
475 	rst_data->sysc = sysc;  in mt7621_reset_init()
476 	rst_data->rcdev.ops = &reset_ops;  in mt7621_reset_init()
477 	rst_data->rcdev.owner = THIS_MODULE;  in mt7621_reset_init()
478 	rst_data->rcdev.nr_resets = 32;  in mt7621_reset_init()
479 	rst_data->rcdev.of_reset_n_cells = 1;  in mt7621_reset_init()
480 	rst_data->rcdev.of_xlate = mt7621_rst_xlate;  in mt7621_reset_init()
481 	rst_data->rcdev.of_node = dev_of_node(dev);  in mt7621_reset_init()
483 	return devm_reset_controller_register(dev, &rst_data->rcdev);  in mt7621_reset_init()
488 	struct device_node *np = pdev->dev.of_node;  in mt7621_clk_probe()
490 	struct device *dev = &pdev->dev;  in mt7621_clk_probe()
496 		return -ENOMEM;  in mt7621_clk_probe()
498 	priv->sysc = syscon_node_to_regmap(np);  in mt7621_clk_probe()
499 	if (IS_ERR(priv->sysc)) {  in mt7621_clk_probe()
500 		ret = PTR_ERR(priv->sysc);  in mt7621_clk_probe()
505 	priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl");  in mt7621_clk_probe()
506 	if (IS_ERR(priv->memc)) {  in mt7621_clk_probe()
507 		ret = PTR_ERR(priv->memc);  in mt7621_clk_probe()
508 		dev_err(dev, "Could not get memc syscon regmap\n");  in mt7621_clk_probe()
512 	ret = mt7621_reset_init(dev, priv->sysc);  in mt7621_clk_probe()
523 		return -ENOMEM;  in mt7621_clk_probe()
524 	clk_data->num = count;  in mt7621_clk_probe()
527 		clk_data->hws[i] = mt7621_clk_early[i];  in mt7621_clk_probe()
553 		clk_hw_unregister(&sclk->hw);  in mt7621_clk_probe()
560 		clk_hw_unregister_fixed_rate(sclk->hw);  in mt7621_clk_probe()
567 	{ .compatible = "mediatek,mt7621-sysc" },
574 		.name = "mt7621-clk",