Lines Matching +full:0 +full:x850
28 { 249600000, 2000000000, 0 },
32 .l = 0x14,
33 .alpha = 0xD555,
34 .config_ctl_val = 0x20485699,
35 .config_ctl_hi_val = 0x00002267,
36 .config_ctl_hi1_val = 0x00000024,
37 .test_ctl_hi1_val = 0x00000020,
38 .user_ctl_val = 0x00000000,
39 .user_ctl_hi_val = 0x00000805,
40 .user_ctl_hi1_val = 0x000000D0,
44 .offset = 0x42c,
61 { P_BI_TCXO, 0 },
71 F(19200000, P_BI_TCXO, 1, 0, 0),
72 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
73 F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
74 F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
75 F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
76 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
77 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
82 .cmd_rcgr = 0x7f0,
83 .mnd_width = 0,
97 .halt_reg = 0x8f4,
100 .enable_reg = 0x8f4,
101 .enable_mask = BIT(0),
115 .halt_reg = 0x890,
118 .enable_reg = 0x890,
119 .enable_mask = BIT(0),
133 .halt_reg = 0x8d0,
136 .enable_reg = 0x8d0,
137 .enable_mask = BIT(0),
151 .halt_reg = 0x850,
154 .enable_reg = 0x850,
155 .enable_mask = BIT(0),
169 .gdscr = 0x814,
173 .flags = 0,
178 .gdscr = 0x874,
187 .gdscr = 0x8b4,
213 .max_register = 0xb94,
218 [VIDEO_CC_MVSC_CORE_CLK_BCR] = { .reg = 0x850, .bit = 2, .udelay = 150 },
219 [VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
220 [VIDEO_CC_MVS0_BCR] = { 0x870 },
221 [VIDEO_CC_MVS1_BCR] = { 0x8b0 },
222 [VIDEO_CC_MVSC_BCR] = { 0x810 },
263 regmap_update_bits(regmap, 0x984, 0x1, 0x1); in video_cc_sm8150_probe()