Lines Matching +full:0 +full:x850
36 { 249600000, 2000000000, 0 },
41 .l = 0x19,
42 .alpha = 0x0,
43 .config_ctl_val = 0x20485699,
44 .config_ctl_hi_val = 0x00002067,
45 .user_ctl_val = 0x00000001,
46 .user_ctl_hi_val = 0x00004805,
47 .test_ctl_hi_val = 0x40000000,
51 .offset = 0x42c,
68 { P_BI_TCXO, 0 },
82 { P_BI_TCXO, 0 },
90 F(240000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
91 F(338000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
92 F(365000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
93 F(444000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
94 F(533000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
99 .cmd_rcgr = 0x7f0,
100 .mnd_width = 0,
114 F(19200000, P_BI_TCXO, 1, 0, 0),
119 .cmd_rcgr = 0xa98,
120 .mnd_width = 0,
133 .halt_reg = 0x8f4,
136 .enable_reg = 0x8f4,
137 .enable_mask = BIT(0),
151 .halt_reg = 0x9ec,
154 .enable_reg = 0x9ec,
155 .enable_mask = BIT(0),
164 .halt_reg = 0x890,
167 .enable_reg = 0x890,
168 .enable_mask = BIT(0),
182 .halt_reg = 0xa0c,
185 .enable_reg = 0xa0c,
186 .enable_mask = BIT(0),
195 .halt_reg = 0x8d0,
198 .enable_reg = 0x8d0,
199 .enable_mask = BIT(0),
213 .halt_reg = 0x850,
216 .enable_reg = 0x850,
217 .enable_mask = BIT(0),
231 .halt_reg = 0x9cc,
234 .enable_reg = 0x9cc,
235 .enable_mask = BIT(0),
244 .halt_reg = 0xa6c,
247 .enable_reg = 0xa6c,
248 .enable_mask = BIT(0),
257 .gdscr = 0x814,
261 .cxcs = (unsigned int []){ 0x850, 0x9cc },
268 .gdscr = 0x874,
272 .cxcs = (unsigned int []){ 0x890, 0x9ec },
279 .gdscr = 0x8b4,
283 .cxcs = (unsigned int []){ 0x8d0, 0xa0c },
313 .max_register = 0xb94,
342 qcom_branch_set_clk_en(regmap, 0x984); /* VIDEOCC_XO_CLK */ in videocc_sm7150_probe()