Lines Matching +full:0 +full:x850
29 .l = 0x10,
30 .alpha = 0xaaab,
34 .offset = 0x42c,
49 { P_BI_TCXO, 0 },
63 F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
64 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
65 F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
66 F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
67 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
68 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
73 .cmd_rcgr = 0x7f0,
74 .mnd_width = 0,
88 .halt_reg = 0x990,
91 .enable_reg = 0x990,
92 .enable_mask = BIT(0),
101 .halt_reg = 0x9f0,
104 .enable_reg = 0x9f0,
105 .enable_mask = BIT(0),
114 .halt_reg = 0x970,
117 .enable_reg = 0x970,
118 .enable_mask = BIT(0),
127 .halt_reg = 0x9d0,
130 .enable_reg = 0x9d0,
131 .enable_mask = BIT(0),
140 .halt_reg = 0x930,
143 .enable_reg = 0x930,
144 .enable_mask = BIT(0),
153 .halt_reg = 0x890,
156 .enable_reg = 0x890,
157 .enable_mask = BIT(0),
171 .halt_reg = 0x950,
174 .enable_reg = 0x950,
175 .enable_mask = BIT(0),
184 .halt_reg = 0x8d0,
187 .enable_reg = 0x8d0,
188 .enable_mask = BIT(0),
202 .halt_reg = 0x9b0,
205 .enable_reg = 0x9b0,
206 .enable_mask = BIT(0),
215 .halt_reg = 0x910,
218 .enable_reg = 0x910,
219 .enable_mask = BIT(0),
228 .halt_reg = 0x850,
231 .enable_reg = 0x850,
232 .enable_mask = BIT(0),
246 .gdscr = 0x814,
250 .cxcs = (unsigned int []){ 0x850, 0x910 },
257 .gdscr = 0x874,
261 .cxcs = (unsigned int []){ 0x890, 0x930 },
268 .gdscr = 0x8b4,
272 .cxcs = (unsigned int []){ 0x8d0, 0x950 },
304 .max_register = 0xb90,