Lines Matching +full:0 +full:x1c000

23 	.halt_reg = 0x1b004,
26 		.enable_reg = 0x1b004,
27 		.enable_mask = BIT(0),
36 	.halt_reg = 0x22000,
39 		.enable_reg = 0x22000,
40 		.enable_mask = BIT(0),
49 	.halt_reg = 0x1c000,
52 		.enable_reg = 0x1c000,
53 		.enable_mask = BIT(0),
62 	.halt_reg = 0x22004,
65 		.enable_reg = 0x22004,
66 		.enable_mask = BIT(0),
75 	.halt_reg = 0x1c004,
78 		.enable_reg = 0x1c004,
79 		.enable_mask = BIT(0),
88 	.halt_reg = 0x6004,
91 		.enable_reg = 0x6004,
92 		.enable_mask = BIT(0),
102 	.halt_reg = 0x8008,
105 		.enable_reg = 0x8008,
106 		.enable_mask = BIT(0),
131 	[Q6SSTOP_BCR_RESET] = { 0x6000 },
172 	if (ret < 0) {  in q6sstopcc_qcs404_probe()
191 	ret = qcom_cc_probe_by_index(pdev, 0, desc);  in q6sstopcc_qcs404_probe()
197 	return 0;  in q6sstopcc_qcs404_probe()