Lines Matching +full:0 +full:x3220
49 { 0x0, 1 },
50 { 0x1, 2 },
51 { 0x3, 4 },
52 { 0x7, 8 },
57 .offset = 0xc000,
60 .enable_reg = 0x1e0,
61 .enable_mask = BIT(0),
74 .offset = 0xc000,
89 .offset = 0xc050,
92 .enable_reg = 0x1e0,
106 .offset = 0xc050,
121 .offset = 0x0,
134 .offset = 0x0,
149 .offset = 0x50,
162 .offset = 0x50,
177 .offset = 0xa0,
190 .offset = 0xa0,
205 .offset = 0xf0,
218 .offset = 0xf0,
233 .offset = 0x140,
246 .offset = 0x140,
261 .offset = 0x190,
274 .offset = 0x190,
289 { P_XO, 0 },
299 { P_XO, 0 },
311 { P_XO, 0 },
323 { P_XO, 0 },
335 { P_XO, 0 },
347 { P_XO, 0 },
361 { P_XO, 0 },
377 { P_XO, 0 },
393 { P_XO, 0 },
411 { P_XO, 0 },
429 { P_XO, 0 },
447 { P_XO, 0 },
467 .cmd_rcgr = 0x2120,
480 .cmd_rcgr = 0x2140,
493 F(37500000, P_GPLL0, 16, 0, 0),
494 F(50000000, P_GPLL0, 12, 0, 0),
495 F(100000000, P_GPLL0, 6, 0, 0),
500 .cmd_rcgr = 0x3300,
513 F(100000000, P_GPLL0, 6, 0, 0),
514 F(200000000, P_GPLL0, 3, 0, 0),
515 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
516 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
517 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
518 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
519 F(600000000, P_GPLL0, 1, 0, 0),
524 .cmd_rcgr = 0x3640,
537 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
538 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
539 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
540 F(300000000, P_GPLL0, 2, 0, 0),
541 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
542 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
547 .cmd_rcgr = 0x3090,
560 .cmd_rcgr = 0x3100,
573 .cmd_rcgr = 0x3160,
586 .cmd_rcgr = 0x31c0,
599 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
600 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
601 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
602 F(300000000, P_GPLL0, 2, 0, 0),
603 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
608 .cmd_rcgr = 0x3800,
621 F(200000000, P_GPLL0, 3, 0, 0),
622 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
627 .cmd_rcgr = 0x3000,
640 .cmd_rcgr = 0x3030,
653 .cmd_rcgr = 0x3060,
666 F(19200000, P_XO, 1, 0, 0),
671 .cmd_rcgr = 0x2260,
691 .cmd_rcgr = 0x2220,
704 F(162000, P_DPLINK, 2, 0, 0),
705 F(270000, P_DPLINK, 2, 0, 0),
706 F(540000, P_DPLINK, 2, 0, 0),
711 .cmd_rcgr = 0x2200,
724 F(154000000, P_DPVCO, 1, 0, 0),
725 F(337500000, P_DPVCO, 2, 0, 0),
726 F(675000000, P_DPVCO, 2, 0, 0),
731 .cmd_rcgr = 0x2240,
744 F(19200000, P_XO, 1, 0, 0),
749 .cmd_rcgr = 0x2160,
762 .cmd_rcgr = 0x2180,
780 .cmd_rcgr = 0x2060,
794 F(100000000, P_GPLL0, 6, 0, 0),
795 F(200000000, P_GPLL0, 3, 0, 0),
796 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
797 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
798 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
803 .cmd_rcgr = 0x3b00,
816 F(19200000, P_XO, 1, 0, 0),
821 .cmd_rcgr = 0x2100,
834 F(75000000, P_GPLL0, 8, 0, 0),
835 F(150000000, P_GPLL0, 4, 0, 0),
836 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
837 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
842 .cmd_rcgr = 0x3500,
855 F(19200000, P_XO, 1, 0, 0),
856 F(75000000, P_GPLL0_DIV, 4, 0, 0),
857 F(171428571, P_GPLL0, 3.5, 0, 0),
858 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
859 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
864 .cmd_rcgr = 0xf020,
877 F(4800000, P_XO, 4, 0, 0),
880 F(9600000, P_XO, 2, 0, 0),
882 F(19200000, P_XO, 1, 0, 0),
891 .cmd_rcgr = 0x3360,
904 .cmd_rcgr = 0x3390,
917 .cmd_rcgr = 0x33c0,
930 .cmd_rcgr = 0x33f0,
943 F(85714286, P_GPLL0, 7, 0, 0),
944 F(100000000, P_GPLL0, 6, 0, 0),
945 F(150000000, P_GPLL0, 4, 0, 0),
946 F(171428571, P_GPLL0, 3.5, 0, 0),
947 F(200000000, P_GPLL0, 3, 0, 0),
948 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
949 F(300000000, P_GPLL0, 2, 0, 0),
950 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
951 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
956 .cmd_rcgr = 0x2040,
969 F(19200000, P_XO, 1, 0, 0),
974 .cmd_rcgr = 0x2080,
987 F(19200000, P_XO, 1, 0, 0),
988 F(40000000, P_GPLL0, 15, 0, 0),
989 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
994 .cmd_rcgr = 0x5000,
1007 F(75000000, P_GPLL0, 8, 0, 0),
1008 F(171428571, P_GPLL0, 3.5, 0, 0),
1009 F(240000000, P_GPLL0, 2.5, 0, 0),
1010 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1011 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1017 .cmd_rcgr = 0xd000,
1030 .cmd_rcgr = 0x2000,
1044 .cmd_rcgr = 0x2020,
1058 F(171428571, P_GPLL0, 3.5, 0, 0),
1059 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1060 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1061 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1066 .cmd_rcgr = 0x21a0,
1079 F(200000000, P_GPLL0, 3, 0, 0),
1080 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1081 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1082 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1083 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1088 .cmd_rcgr = 0x1000,
1101 .cmd_rcgr = 0x1060,
1114 .cmd_rcgr = 0x1080,
1127 F(200000000, P_GPLL0, 3, 0, 0),
1128 F(300000000, P_GPLL0, 2, 0, 0),
1129 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1130 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1131 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1132 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1133 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1134 F(600000000, P_GPLL0, 1, 0, 0),
1139 .cmd_rcgr = 0x3600,
1152 .cmd_rcgr = 0x3620,
1165 .halt_reg = 0x328,
1166 .hwcg_reg = 0x328,
1169 .enable_reg = 0x328,
1170 .enable_mask = BIT(0),
1182 .halt_reg = 0x1028,
1184 .enable_reg = 0x1028,
1185 .enable_mask = BIT(0),
1197 .halt_reg = 0x1030,
1198 .hwcg_reg = 0x1030,
1201 .enable_reg = 0x1030,
1202 .enable_mask = BIT(0),
1214 .halt_reg = 0x1034,
1216 .enable_reg = 0x1034,
1217 .enable_mask = BIT(0),
1228 .halt_reg = 0x1038,
1230 .enable_reg = 0x1038,
1231 .enable_mask = BIT(0),
1243 .halt_reg = 0x1048,
1245 .enable_reg = 0x1048,
1246 .enable_mask = BIT(0),
1258 .halt_reg = 0x104c,
1260 .enable_reg = 0x104c,
1261 .enable_mask = BIT(0),
1273 .halt_reg = 0x2308,
1274 .hwcg_reg = 0x2308,
1277 .enable_reg = 0x2308,
1278 .enable_mask = BIT(0),
1290 .halt_reg = 0x230c,
1292 .enable_reg = 0x230c,
1293 .enable_mask = BIT(0),
1305 .halt_reg = 0x2310,
1307 .enable_reg = 0x2310,
1308 .enable_mask = BIT(0),
1319 .halt_reg = 0x2314,
1321 .enable_reg = 0x2314,
1322 .enable_mask = BIT(0),
1334 .halt_reg = 0x2318,
1336 .enable_reg = 0x2318,
1337 .enable_mask = BIT(0),
1349 .halt_reg = 0x231c,
1351 .enable_reg = 0x231c,
1352 .enable_mask = BIT(0),
1364 .halt_reg = 0x2320,
1366 .enable_reg = 0x2320,
1367 .enable_mask = BIT(0),
1379 .halt_reg = 0x2324,
1381 .enable_reg = 0x2324,
1382 .enable_mask = BIT(0),
1394 .halt_reg = 0x2328,
1396 .enable_reg = 0x2328,
1397 .enable_mask = BIT(0),
1409 .halt_reg = 0x2338,
1411 .enable_reg = 0x2338,
1412 .enable_mask = BIT(0),
1424 .halt_reg = 0x233c,
1426 .enable_reg = 0x233c,
1427 .enable_mask = BIT(0),
1439 .halt_reg = 0x2340,
1441 .enable_reg = 0x2340,
1442 .enable_mask = BIT(0),
1454 .halt_reg = 0x2344,
1456 .enable_reg = 0x2344,
1457 .enable_mask = BIT(0),
1469 .halt_reg = 0x2348,
1471 .enable_reg = 0x2348,
1472 .enable_mask = BIT(0),
1484 .halt_reg = 0x2350,
1486 .enable_reg = 0x2350,
1487 .enable_mask = BIT(0),
1499 .halt_reg = 0x2354,
1501 .enable_reg = 0x2354,
1502 .enable_mask = BIT(0),
1514 .halt_reg = 0x2358,
1516 .enable_reg = 0x2358,
1517 .enable_mask = BIT(0),
1529 .halt_reg = 0x235c,
1531 .enable_reg = 0x235c,
1532 .enable_mask = BIT(0),
1544 .halt_reg = 0x2360,
1546 .enable_reg = 0x2360,
1547 .enable_mask = BIT(0),
1559 .halt_reg = 0x2364,
1561 .enable_reg = 0x2364,
1562 .enable_mask = BIT(0),
1574 .halt_reg = 0x2374,
1576 .enable_reg = 0x2374,
1577 .enable_mask = BIT(0),
1589 .halt_reg = 0x2378,
1591 .enable_reg = 0x2378,
1592 .enable_mask = BIT(0),
1604 .halt_reg = 0x3024,
1606 .enable_reg = 0x3024,
1607 .enable_mask = BIT(0),
1619 .halt_reg = 0x3054,
1621 .enable_reg = 0x3054,
1622 .enable_mask = BIT(0),
1634 .halt_reg = 0x3084,
1636 .enable_reg = 0x3084,
1637 .enable_mask = BIT(0),
1649 .halt_reg = 0x30b4,
1651 .enable_reg = 0x30b4,
1652 .enable_mask = BIT(0),
1664 .halt_reg = 0x30bc,
1666 .enable_reg = 0x30bc,
1667 .enable_mask = BIT(0),
1679 .halt_reg = 0x30d4,
1681 .enable_reg = 0x30d4,
1682 .enable_mask = BIT(0),
1694 .halt_reg = 0x30e4,
1696 .enable_reg = 0x30e4,
1697 .enable_mask = BIT(0),
1709 .halt_reg = 0x3124,
1711 .enable_reg = 0x3124,
1712 .enable_mask = BIT(0),
1724 .halt_reg = 0x3128,
1726 .enable_reg = 0x3128,
1727 .enable_mask = BIT(0),
1739 .halt_reg = 0x3144,
1741 .enable_reg = 0x3144,
1742 .enable_mask = BIT(0),
1754 .halt_reg = 0x3154,
1756 .enable_reg = 0x3154,
1757 .enable_mask = BIT(0),
1769 .halt_reg = 0x3184,
1771 .enable_reg = 0x3184,
1772 .enable_mask = BIT(0),
1784 .halt_reg = 0x3188,
1786 .enable_reg = 0x3188,
1787 .enable_mask = BIT(0),
1799 .halt_reg = 0x31a4,
1801 .enable_reg = 0x31a4,
1802 .enable_mask = BIT(0),
1814 .halt_reg = 0x31b4,
1816 .enable_reg = 0x31b4,
1817 .enable_mask = BIT(0),
1829 .halt_reg = 0x31e4,
1831 .enable_reg = 0x31e4,
1832 .enable_mask = BIT(0),
1844 .halt_reg = 0x31e8,
1846 .enable_reg = 0x31e8,
1847 .enable_mask = BIT(0),
1859 .halt_reg = 0x3204,
1861 .enable_reg = 0x3204,
1862 .enable_mask = BIT(0),
1874 .halt_reg = 0x3214,
1876 .enable_reg = 0x3214,
1877 .enable_mask = BIT(0),
1889 .halt_reg = 0x3224,
1891 .enable_reg = 0x3224,
1892 .enable_mask = BIT(0),
1904 .halt_reg = 0x3344,
1906 .enable_reg = 0x3344,
1907 .enable_mask = BIT(0),
1919 .halt_reg = 0x3348,
1921 .enable_reg = 0x3348,
1922 .enable_mask = BIT(0),
1934 .halt_reg = 0x3384,
1936 .enable_reg = 0x3384,
1937 .enable_mask = BIT(0),
1949 .halt_reg = 0x33b4,
1951 .enable_reg = 0x33b4,
1952 .enable_mask = BIT(0),
1964 .halt_reg = 0x33e4,
1966 .enable_reg = 0x33e4,
1967 .enable_mask = BIT(0),
1979 .halt_reg = 0x3414,
1981 .enable_reg = 0x3414,
1982 .enable_mask = BIT(0),
1994 .halt_reg = 0x3484,
1996 .enable_reg = 0x3484,
1997 .enable_mask = BIT(0),
2009 .halt_reg = 0x348c,
2011 .enable_reg = 0x348c,
2012 .enable_mask = BIT(0),
2024 .halt_reg = 0x3494,
2026 .enable_reg = 0x3494,
2027 .enable_mask = BIT(0),
2039 .halt_reg = 0x35a8,
2041 .enable_reg = 0x35a8,
2042 .enable_mask = BIT(0),
2054 .halt_reg = 0x35b4,
2056 .enable_reg = 0x35b4,
2057 .enable_mask = BIT(0),
2069 .halt_reg = 0x35b8,
2071 .enable_reg = 0x35b8,
2072 .enable_mask = BIT(0),
2083 .halt_reg = 0x3668,
2085 .enable_reg = 0x3668,
2086 .enable_mask = BIT(0),
2098 .halt_reg = 0x3678,
2100 .enable_reg = 0x3678,
2101 .enable_mask = BIT(0),
2113 .halt_reg = 0x36a8,
2115 .enable_reg = 0x36a8,
2116 .enable_mask = BIT(0),
2128 .halt_reg = 0x36ac,
2130 .enable_reg = 0x36ac,
2131 .enable_mask = BIT(0),
2143 .halt_reg = 0x36b0,
2145 .enable_reg = 0x36b0,
2146 .enable_mask = BIT(0),
2158 .halt_reg = 0x36b4,
2160 .enable_reg = 0x36b4,
2161 .enable_mask = BIT(0),
2173 .halt_reg = 0x36b8,
2175 .enable_reg = 0x36b8,
2176 .enable_mask = BIT(0),
2188 .halt_reg = 0x36bc,
2190 .enable_reg = 0x36bc,
2191 .enable_mask = BIT(0),
2202 .halt_reg = 0x36c4,
2204 .enable_reg = 0x36c4,
2205 .enable_mask = BIT(0),
2216 .halt_reg = 0x36c8,
2218 .enable_reg = 0x36c8,
2219 .enable_mask = BIT(0),
2231 .halt_reg = 0x3704,
2233 .enable_reg = 0x3704,
2234 .enable_mask = BIT(0),
2246 .halt_reg = 0x3714,
2248 .enable_reg = 0x3714,
2249 .enable_mask = BIT(0),
2261 .halt_reg = 0x3720,
2263 .enable_reg = 0x3720,
2264 .enable_mask = BIT(0),
2276 .halt_reg = 0x3724,
2278 .enable_reg = 0x3724,
2279 .enable_mask = BIT(0),
2291 .halt_reg = 0x3730,
2293 .enable_reg = 0x3730,
2294 .enable_mask = BIT(0),
2306 .halt_reg = 0x3734,
2308 .enable_reg = 0x3734,
2309 .enable_mask = BIT(0),
2321 .halt_reg = 0x3738,
2323 .enable_reg = 0x3738,
2324 .enable_mask = BIT(0),
2336 .halt_reg = 0x373c,
2338 .enable_reg = 0x373c,
2339 .enable_mask = BIT(0),
2351 .halt_reg = 0x3740,
2353 .enable_reg = 0x3740,
2354 .enable_mask = BIT(0),
2366 .halt_reg = 0x3744,
2368 .enable_reg = 0x3744,
2369 .enable_mask = BIT(0),
2381 .halt_reg = 0x3748,
2383 .enable_reg = 0x3748,
2384 .enable_mask = BIT(0),
2396 .halt_reg = 0x3b68,
2398 .enable_reg = 0x3b68,
2399 .enable_mask = BIT(0),
2411 .halt_reg = 0x3b6c,
2413 .enable_reg = 0x3b6c,
2414 .enable_mask = BIT(0),
2426 .halt_reg = 0x3b74,
2428 .enable_reg = 0x3b74,
2429 .enable_mask = BIT(0),
2441 .halt_reg = 0x5024,
2444 .enable_reg = 0x5024,
2445 .enable_mask = BIT(0),
2457 .halt_reg = 0xe004,
2459 .hwcg_reg = 0xe004,
2462 .enable_reg = 0xe004,
2463 .enable_mask = BIT(0),
2475 .halt_reg = 0xe008,
2477 .hwcg_reg = 0xe008,
2480 .enable_reg = 0xe008,
2481 .enable_mask = BIT(0),
2492 .halt_reg = 0xf004,
2494 .enable_reg = 0xf004,
2495 .enable_mask = BIT(0),
2507 .halt_reg = 0xf064,
2509 .enable_reg = 0xf064,
2510 .enable_mask = BIT(0),
2522 .halt_reg = 0xf068,
2524 .enable_reg = 0xf068,
2525 .enable_mask = BIT(0),
2537 .gdscr = 0x1024,
2538 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2547 .gdscr = 0x1040,
2548 .cxcs = (unsigned int []){ 0x1048 },
2559 .gdscr = 0x1044,
2560 .cxcs = (unsigned int []){ 0x104c },
2571 .gdscr = 0x2304,
2572 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2581 .gdscr = 0x34a0,
2582 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2583 0x35a8, 0x3868 },
2592 .gdscr = 0x3664,
2601 .gdscr = 0x3674,
2610 .gdscr = 0x36d4,
2619 .gdscr = 0xe020,
2620 .gds_hw_ctrl = 0xe024,
2621 .cxcs = (unsigned int []){ 0xe008 },
2792 [SPDM_BCR] = { 0x200 },
2793 [SPDM_RM_BCR] = { 0x300 },
2794 [MISC_BCR] = { 0x320 },
2795 [VIDEO_TOP_BCR] = { 0x1020 },
2796 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2797 [MDSS_BCR] = { 0x2300 },
2798 [THROTTLE_MDSS_BCR] = { 0x2460 },
2799 [CAMSS_PHY0_BCR] = { 0x3020 },
2800 [CAMSS_PHY1_BCR] = { 0x3050 },
2801 [CAMSS_PHY2_BCR] = { 0x3080 },
2802 [CAMSS_CSI0_BCR] = { 0x30b0 },
2803 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2804 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2805 [CAMSS_CSI1_BCR] = { 0x3120 },
2806 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2807 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2808 [CAMSS_CSI2_BCR] = { 0x3180 },
2809 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2810 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2811 [CAMSS_CSI3_BCR] = { 0x31e0 },
2812 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2813 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2814 [CAMSS_ISPIF_BCR] = { 0x3220 },
2815 [CAMSS_CCI_BCR] = { 0x3340 },
2816 [CAMSS_TOP_BCR] = { 0x3480 },
2817 [CAMSS_AHB_BCR] = { 0x3488 },
2818 [CAMSS_MICRO_BCR] = { 0x3490 },
2819 [CAMSS_JPEG_BCR] = { 0x35a0 },
2820 [CAMSS_VFE0_BCR] = { 0x3660 },
2821 [CAMSS_VFE1_BCR] = { 0x3670 },
2822 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2823 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2824 [CAMSS_CPP_BCR] = { 0x36d0 },
2825 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2826 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2827 [CAMSS_FD_BCR] = { 0x3b60 },
2828 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2829 [MNOCAHB_BCR] = { 0x5020 },
2830 [MNOCAXI_BCR] = { 0xd020 },
2831 [BMIC_SMMU_BCR] = { 0xe000 },
2832 [MNOC_MAXI_BCR] = { 0xf000 },
2833 [VMEM_BCR] = { 0xf060 },
2834 [BTO_BCR] = { 0x10004 },
2841 .max_register = 0x10004,