Lines Matching +full:0 +full:x0210
46 .l_reg = 0x320,
47 .m_reg = 0x324,
48 .n_reg = 0x328,
49 .config_reg = 0x32c,
50 .mode_reg = 0x31c,
51 .status_reg = 0x334,
64 .l_reg = 0x33c,
65 .m_reg = 0x340,
66 .n_reg = 0x344,
67 .config_reg = 0x348,
68 .mode_reg = 0x338,
69 .status_reg = 0x350,
85 .vco_val = 0x2 << 16,
86 .vco_mask = 0x3 << 16,
87 .pre_div_val = 0x0,
89 .post_div_val = 0x0,
90 .post_div_mask = 0x3 << 20,
96 { P_PXO, 0 },
108 { P_PXO, 0 },
122 { P_PXO, 0 },
136 { P_PXO, 0 },
148 { P_PXO, 0 },
162 { P_PXO, 0 },
183 { 96000000, P_PLL8, 4, 0, 0 },
184 { 128000000, P_PLL8, 3, 0, 0 },
189 .ns_reg = 0x0148,
190 .md_reg = 0x0144,
205 .src_sel_shift = 0,
210 .enable_reg = 0x0140,
222 .halt_reg = 0x01e8,
225 .enable_reg = 0x0140,
226 .enable_mask = BIT(0),
240 .ns_reg = 0x015c,
241 .md_reg = 0x0158,
256 .src_sel_shift = 0,
261 .enable_reg = 0x0154,
273 .halt_reg = 0x01e8,
276 .enable_reg = 0x0154,
277 .enable_mask = BIT(0),
291 .ns_reg = 0x0228,
292 .md_reg = 0x0224,
307 .src_sel_shift = 0,
312 .enable_reg = 0x0220,
324 .halt_reg = 0x01e8,
327 .enable_reg = 0x0220,
328 .enable_mask = BIT(0),
342 { 27000000, P_PXO, 1, 0, 0 },
349 .ns_reg = 0x0048,
350 .md_reg = 0x0044,
364 .src_sel_shift = 0,
369 .enable_reg = 0x0040,
381 .halt_reg = 0x01cc,
384 .enable_reg = 0x0040,
385 .enable_mask = BIT(0),
399 .halt_reg = 0x01e8,
402 .enable_reg = 0x0040,
417 .ns_reg = 0x0010,
418 .md_reg = 0x0028,
432 .src_sel_shift = 0,
437 .enable_reg = 0x0024,
449 .halt_reg = 0x01cc,
452 .enable_reg = 0x0024,
453 .enable_mask = BIT(0),
467 .halt_reg = 0x01e8,
470 .enable_reg = 0x0024,
485 .ns_reg = 0x0234,
486 .md_reg = 0x022c,
500 .src_sel_shift = 0,
505 .enable_reg = 0x022c,
517 .halt_reg = 0x01cc,
520 .enable_reg = 0x022c,
521 .enable_mask = BIT(0),
535 .halt_reg = 0x01e8,
538 .enable_reg = 0x022c,
566 int ret = 0; in pix_rdi_set_parent()
579 for (i = 0; i < num_parents; i++) { in pix_rdi_set_parent()
589 val = 0; in pix_rdi_set_parent()
600 val = 0; in pix_rdi_set_parent()
609 for (i--; i >= 0; i--) { in pix_rdi_set_parent()
631 return 0; in pix_rdi_get_parent()
649 .s_reg = 0x0058,
651 .s2_reg = 0x0238,
654 .enable_reg = 0x0058,
666 .s_reg = 0x0238,
668 .s2_reg = 0x0238,
671 .enable_reg = 0x0238,
683 .s_reg = 0x0058,
685 .s2_reg = 0x0238,
688 .enable_reg = 0x0058,
700 .s_reg = 0x0238,
701 .s_mask = BIT(0),
702 .s2_reg = 0x0238,
705 .enable_reg = 0x0238,
717 .s_reg = 0x0238,
719 .s2_reg = 0x0238,
722 .enable_reg = 0x0238,
740 .ns_reg = 0x0168,
741 .md_reg = 0x0164,
756 .src_sel_shift = 0,
761 .enable_reg = 0x0160,
773 .halt_reg = 0x01e8,
776 .enable_reg = 0x0160,
777 .enable_mask = BIT(0),
791 .halt_reg = 0x01e8,
794 .enable_reg = 0x0160,
809 .halt_reg = 0x01e8,
812 .enable_reg = 0x0160,
827 F_MN( 27000000, P_PXO, 1, 0),
843 .ns_reg[0] = 0x0070,
844 .ns_reg[1] = 0x0070,
845 .md_reg[0] = 0x0064,
846 .md_reg[1] = 0x0068,
847 .bank_reg = 0x0060,
848 .mn[0] = {
864 .s[0] = {
869 .src_sel_shift = 0,
875 .enable_reg = 0x0060,
887 .halt_reg = 0x01c8,
890 .enable_reg = 0x0060,
891 .enable_mask = BIT(0),
905 .ns_reg[0] = 0x007c,
906 .ns_reg[1] = 0x007c,
907 .md_reg[0] = 0x0078,
908 .md_reg[1] = 0x006c,
909 .bank_reg = 0x0074,
910 .mn[0] = {
926 .s[0] = {
931 .src_sel_shift = 0,
937 .enable_reg = 0x0074,
949 .halt_reg = 0x01c8,
952 .enable_reg = 0x0074,
953 .enable_mask = BIT(0),
967 F_MN( 27000000, P_PXO, 1, 0),
987 F_MN( 27000000, P_PXO, 0, 0),
1008 .ns_reg[0] = 0x008c,
1009 .ns_reg[1] = 0x008c,
1010 .md_reg[0] = 0x0084,
1011 .md_reg[1] = 0x0088,
1012 .bank_reg = 0x0080,
1013 .mn[0] = {
1029 .s[0] = {
1034 .src_sel_shift = 0,
1040 .enable_reg = 0x0080,
1059 .halt_reg = 0x01c8,
1062 .enable_reg = 0x0080,
1063 .enable_mask = BIT(0),
1077 F_MN( 27000000, P_PXO, 0, 0),
1088 .ns_reg[0] = 0x021c,
1089 .ns_reg[1] = 0x021c,
1090 .md_reg[0] = 0x01ec,
1091 .md_reg[1] = 0x0218,
1092 .bank_reg = 0x0178,
1093 .mn[0] = {
1109 .s[0] = {
1114 .src_sel_shift = 0,
1120 .enable_reg = 0x0178,
1132 .halt_reg = 0x0240,
1135 .enable_reg = 0x0178,
1136 .enable_mask = BIT(0),
1150 .halt_reg = 0x0240,
1153 .enable_reg = 0x0178,
1168 { 27000000, P_PXO, 1, 0, 0 },
1170 { 54860000, P_PLL8, 7, 0, 0 },
1171 { 96000000, P_PLL8, 4, 0, 0 },
1173 { 128000000, P_PLL8, 3, 0, 0 },
1175 { 200000000, P_PLL2, 4, 0, 0 },
1183 .ns_reg = 0x00a0,
1184 .md_reg = 0x009c,
1198 .src_sel_shift = 0,
1203 .enable_reg = 0x0098,
1215 .halt_reg = 0x01c8,
1218 .enable_reg = 0x0098,
1219 .enable_mask = BIT(0),
1242 .ns_reg = 0x00ac,
1248 .src_sel_shift = 0,
1253 .enable_reg = 0x00a4,
1265 .halt_reg = 0x01c8,
1268 .enable_reg = 0x00a4,
1269 .enable_mask = BIT(0),
1285 { 27000000, P_PXO, 1, 0, 0 },
1303 .ns_reg[0] = 0x00d0,
1304 .ns_reg[1] = 0x00d0,
1305 .md_reg[0] = 0x00c4,
1306 .md_reg[1] = 0x00c8,
1307 .bank_reg = 0x00c0,
1308 .mn[0] = {
1324 .s[0] = {
1329 .src_sel_shift = 0,
1335 .enable_reg = 0x00c0,
1347 .halt_reg = 0x01d0,
1350 .enable_reg = 0x00c0,
1351 .enable_mask = BIT(0),
1365 .halt_reg = 0x01e8,
1368 .enable_reg = 0x016c,
1369 .enable_mask = BIT(0),
1383 .halt_reg = 0x01cc,
1386 .enable_reg = 0x0058,
1418 .ns_reg[0] = 0x00e8,
1419 .ns_reg[1] = 0x00e8,
1420 .bank_reg = 0x00e8,
1421 .p[0] = {
1429 .s[0] = {
1440 .enable_reg = 0x00e0,
1452 .halt_reg = 0x01d0,
1455 .enable_reg = 0x00e0,
1456 .enable_mask = BIT(0),
1470 { P_PXO, 0 },
1485 .ns_reg = 0x00f4,
1486 .md_reg = 0x00f0,
1500 .src_sel_shift = 0,
1505 .enable_reg = 0x00ec,
1518 .halt_reg = 0x01d4,
1521 .enable_reg = 0x00ec,
1536 .halt_reg = 0x01d4,
1539 .enable_reg = 0x00ec,
1554 .halt_reg = 0x01d4,
1557 .enable_reg = 0x00ec,
1558 .enable_mask = BIT(0),
1572 .halt_reg = 0x01d4,
1575 .enable_reg = 0x00ec,
1590 .halt_reg = 0x0240,
1593 .enable_reg = 0x0124,
1608 .halt_reg = 0x0240,
1611 .enable_reg = 0x0124,
1626 .halt_reg = 0x01cc,
1629 .enable_reg = 0x005c,
1643 F_MN( 27000000, P_PXO, 1, 0),
1656 .ns_reg[0] = 0x0100,
1657 .ns_reg[1] = 0x0100,
1658 .md_reg[0] = 0x00fc,
1659 .md_reg[1] = 0x0128,
1660 .bank_reg = 0x00f8,
1661 .mn[0] = {
1677 .s[0] = {
1682 .src_sel_shift = 0,
1688 .enable_reg = 0x00f8,
1700 .halt_reg = 0x01d0,
1703 .enable_reg = 0x00f8,
1704 .enable_mask = BIT(0),
1730 .ns_reg = 0x0118,
1736 .src_sel_shift = 0,
1741 .enable_reg = 0x0110,
1753 .halt_reg = 0x01c8,
1756 .enable_reg = 0x0110,
1757 .enable_mask = BIT(0),
1772 { 27000000, P_PXO, 1, 0, 0 },
1792 .ns_reg = 0x0108,
1806 .src_sel_shift = 0,
1811 .enable_reg = 0x0104,
1823 .halt_reg = 0x01cc,
1826 .enable_reg = 0x0104,
1827 .enable_mask = BIT(0),
1841 .halt_reg = 0x01cc,
1844 .enable_reg = 0x0104,
1859 .halt_reg = 0x01d8,
1862 .enable_reg = 0x0018,
1872 .hwcg_reg = 0x0018,
1874 .halt_reg = 0x01d8,
1877 .enable_reg = 0x0018,
1887 .hwcg_reg = 0x0018,
1889 .halt_reg = 0x01d8,
1892 .enable_reg = 0x0018,
1902 .halt_reg = 0x01d8,
1905 .enable_reg = 0x0018,
1915 .hwcg_reg = 0x0114,
1917 .halt_reg = 0x01e8,
1920 .enable_reg = 0x0114,
1930 .hwcg_reg = 0x0114,
1932 .halt_reg = 0x01e8,
1935 .enable_reg = 0x0114,
1945 .hwcg_reg = 0x0018,
1947 .halt_reg = 0x01d8,
1950 .enable_reg = 0x0018,
1960 .halt_reg = 0x01d8,
1961 .halt_bit = 0,
1963 .enable_reg = 0x0018,
1973 .hwcg_reg = 0x0018,
1975 .halt_reg = 0x01d8,
1978 .enable_reg = 0x0018,
1988 .hwcg_reg = 0x0020,
1990 .halt_reg = 0x01d8,
1993 .enable_reg = 0x0020,
2003 .halt_reg = 0x0240,
2005 .hwcg_reg = 0x0244,
2008 .enable_reg = 0x0244,
2018 .hwcg_reg = 0x0020,
2020 .halt_reg = 0x01d8,
2023 .enable_reg = 0x0020,
2033 .hwcg_reg = 0x0244,
2035 .halt_reg = 0x0240,
2038 .enable_reg = 0x0244,
2048 .halt_reg = 0x01dc,
2051 .enable_reg = 0x0008,
2061 .halt_reg = 0x01dc,
2064 .enable_reg = 0x0008,
2074 .halt_reg = 0x01dc,
2077 .enable_reg = 0x0008,
2087 .hwcg_reg = 0x0038,
2089 .halt_reg = 0x01dc,
2092 .enable_reg = 0x0008,
2102 .halt_reg = 0x01d8,
2105 .enable_reg = 0x0008,
2115 .hwcg_reg = 0x0038,
2117 .halt_reg = 0x01dc,
2120 .enable_reg = 0x0008,
2130 .ns_reg = 0x0054,
2131 .md_reg = 0x0050,
2145 .src_sel_shift = 0,
2149 .enable_reg = 0x004c,
2162 .halt_reg = 0x01d0,
2165 .enable_reg = 0x004c,
2166 .enable_mask = BIT(0),
2180 .ns_reg = 0x012c,
2181 .md_reg = 0x00a8,
2195 .src_sel_shift = 0,
2199 .enable_reg = 0x003c,
2212 .halt_reg = 0x01d0,
2215 .enable_reg = 0x003c,
2216 .enable_mask = BIT(0),
2230 .ns_reg = 0x00b0,
2236 .src_sel_shift = 0,
2240 .enable_reg = 0x0090,
2253 .halt_reg = 0x01cc,
2256 .enable_reg = 0x0090,
2257 .enable_mask = BIT(0),
2271 .ns_reg = 0x012c,
2277 .src_sel_shift = 0,
2281 .enable_reg = 0x0130,
2294 .halt_reg = 0x01cc,
2297 .enable_reg = 0x00b4,
2298 .enable_mask = BIT(0),
2312 .ns_reg = 0x0011c,
2318 .src_sel_shift = 0,
2322 .enable_reg = 0x00cc,
2334 .halt_reg = 0x01e8,
2337 .enable_reg = 0x00cc,
2338 .enable_mask = BIT(0),
2352 .ns_reg = 0x0150,
2358 .src_sel_shift = 0,
2362 .enable_reg = 0x013c,
2374 .halt_reg = 0x01e8,
2377 .enable_reg = 0x013c,
2378 .enable_mask = BIT(0),
2392 .ns_reg = 0x0138,
2393 .md_reg = 0x0134,
2407 .src_sel_shift = 0,
2411 .enable_reg = 0x0130,
2423 .halt_reg = 0x01d0,
2426 .enable_reg = 0x0130,
2427 .enable_mask = BIT(0),
2441 .ns_reg = 0x00e4,
2442 .md_reg = 0x00b8,
2456 .src_sel_shift = 0,
2460 .enable_reg = 0x0094,
2473 .enable_reg = 0x0094,
2474 .enable_mask = BIT(0),
2488 .halt_reg = 0x01d0,
2491 .enable_reg = 0x0094,
2492 .enable_mask = 0,
2506 .halt_reg = 0x024c,
2509 .enable_reg = 0x0264,
2524 .hwcg_reg = 0x0038,
2526 .halt_reg = 0x01dc,
2529 .enable_reg = 0x0008,
2539 .hwcg_reg = 0x0038,
2541 .halt_reg = 0x01dc,
2544 .enable_reg = 0x0008,
2554 .hwcg_reg = 0x0038,
2556 .halt_reg = 0x01dc,
2559 .enable_reg = 0x0008,
2569 .hwcg_reg = 0x0038,
2571 .halt_reg = 0x01dc,
2574 .enable_reg = 0x0008,
2584 .hwcg_reg = 0x0038,
2586 .halt_reg = 0x01dc,
2589 .enable_reg = 0x0008,
2599 .halt_reg = 0x01dc,
2602 .enable_reg = 0x0008,
2612 .hwcg_reg = 0x0038,
2614 .halt_reg = 0x01dc,
2617 .enable_reg = 0x0008,
2627 .halt_reg = 0x01dc,
2630 .enable_reg = 0x0008,
2640 .halt_reg = 0x01dc,
2643 .enable_reg = 0x0008,
2653 .halt_reg = 0x01dc,
2656 .enable_reg = 0x0008,
2666 .hwcg_reg = 0x0008,
2668 .halt_reg = 0x01dc,
2671 .enable_reg = 0x0008,
2681 .halt_reg = 0x01dc,
2684 .enable_reg = 0x0008,
2694 .halt_reg = 0x0240,
2697 .enable_reg = 0x0248,
2707 .hwcg_reg = 0x0038,
2709 .halt_reg = 0x01dc,
2712 .enable_reg = 0x0008,
2722 .halt_reg = 0x01dc,
2725 .enable_reg = 0x0008,
2735 .halt_reg = 0x01dc,
2738 .enable_reg = 0x0008,
2856 [VPE_AXI_RESET] = { 0x0208, 15 },
2857 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2858 [MPD_AXI_RESET] = { 0x0208, 13 },
2859 [VFE_AXI_RESET] = { 0x0208, 9 },
2860 [SP_AXI_RESET] = { 0x0208, 8 },
2861 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2862 [ROT_AXI_RESET] = { 0x0208, 6 },
2863 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2864 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2865 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2866 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2867 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2868 [FAB_S0_AXI_RESET] = { 0x0208 },
2869 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2870 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2871 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2872 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2873 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2874 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2875 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2876 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2877 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2878 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2879 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2880 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2881 [APU_AHB_RESET] = { 0x020c, 18 },
2882 [CSI_AHB_RESET] = { 0x020c, 17 },
2883 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2884 [VPE_AHB_RESET] = { 0x020c, 14 },
2885 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2886 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2887 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2888 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2889 [HDMI_AHB_RESET] = { 0x020c, 9 },
2890 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2891 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2892 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2893 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2894 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2895 [MDP_AHB_RESET] = { 0x020c, 3 },
2896 [ROT_AHB_RESET] = { 0x020c, 2 },
2897 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2898 [VFE_AHB_RESET] = { 0x020c, 0 },
2899 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2900 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2901 [CSIPHY2_RESET] = { 0x0210, 29 },
2902 [CSI_PIX1_RESET] = { 0x0210, 28 },
2903 [CSIPHY0_RESET] = { 0x0210, 27 },
2904 [CSIPHY1_RESET] = { 0x0210, 26 },
2905 [DSI2_RESET] = { 0x0210, 25 },
2906 [VFE_CSI_RESET] = { 0x0210, 24 },
2907 [MDP_RESET] = { 0x0210, 21 },
2908 [AMP_RESET] = { 0x0210, 20 },
2909 [JPEGD_RESET] = { 0x0210, 19 },
2910 [CSI1_RESET] = { 0x0210, 18 },
2911 [VPE_RESET] = { 0x0210, 17 },
2912 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2913 [VFE_RESET] = { 0x0210, 15 },
2914 [GFX2D0_RESET] = { 0x0210, 14 },
2915 [GFX2D1_RESET] = { 0x0210, 13 },
2916 [GFX3D_RESET] = { 0x0210, 12 },
2917 [HDMI_RESET] = { 0x0210, 11 },
2918 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2919 [IJPEG_RESET] = { 0x0210, 9 },
2920 [CSI0_RESET] = { 0x0210, 8 },
2921 [DSI_RESET] = { 0x0210, 7 },
2922 [VCODEC_RESET] = { 0x0210, 6 },
2923 [MDP_TV_RESET] = { 0x0210, 4 },
2924 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2925 [ROT_RESET] = { 0x0210, 2 },
2926 [TV_HDMI_RESET] = { 0x0210, 1 },
2927 [TV_ENC_RESET] = { 0x0210 },
2928 [CSI2_RESET] = { 0x0214, 2 },
2929 [CSI_RDI1_RESET] = { 0x0214, 1 },
2930 [CSI_RDI2_RESET] = { 0x0214 },
3042 [GFX3D_AXI_RESET] = { 0x0208, 17 },
3043 [VCAP_AXI_RESET] = { 0x0208, 16 },
3044 [VPE_AXI_RESET] = { 0x0208, 15 },
3045 [IJPEG_AXI_RESET] = { 0x0208, 14 },
3046 [MPD_AXI_RESET] = { 0x0208, 13 },
3047 [VFE_AXI_RESET] = { 0x0208, 9 },
3048 [SP_AXI_RESET] = { 0x0208, 8 },
3049 [VCODEC_AXI_RESET] = { 0x0208, 7 },
3050 [ROT_AXI_RESET] = { 0x0208, 6 },
3051 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
3052 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
3053 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
3054 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
3055 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
3056 [FAB_S0_AXI_RESET] = { 0x0208 },
3057 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
3058 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
3059 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
3060 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
3061 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
3062 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
3063 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
3064 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
3065 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
3066 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
3067 [APU_AHB_RESET] = { 0x020c, 18 },
3068 [CSI_AHB_RESET] = { 0x020c, 17 },
3069 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
3070 [VPE_AHB_RESET] = { 0x020c, 14 },
3071 [FABRIC_AHB_RESET] = { 0x020c, 13 },
3072 [GFX3D_AHB_RESET] = { 0x020c, 10 },
3073 [HDMI_AHB_RESET] = { 0x020c, 9 },
3074 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
3075 [IJPEG_AHB_RESET] = { 0x020c, 7 },
3076 [DSI_M_AHB_RESET] = { 0x020c, 6 },
3077 [DSI_S_AHB_RESET] = { 0x020c, 5 },
3078 [JPEGD_AHB_RESET] = { 0x020c, 4 },
3079 [MDP_AHB_RESET] = { 0x020c, 3 },
3080 [ROT_AHB_RESET] = { 0x020c, 2 },
3081 [VCODEC_AHB_RESET] = { 0x020c, 1 },
3082 [VFE_AHB_RESET] = { 0x020c, 0 },
3083 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
3084 [VCAP_AHB_RESET] = { 0x0200, 2 },
3085 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
3086 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
3087 [CSIPHY2_RESET] = { 0x0210, 31 },
3088 [CSI_PIX1_RESET] = { 0x0210, 30 },
3089 [CSIPHY0_RESET] = { 0x0210, 29 },
3090 [CSIPHY1_RESET] = { 0x0210, 28 },
3091 [CSI_RDI_RESET] = { 0x0210, 27 },
3092 [CSI_PIX_RESET] = { 0x0210, 26 },
3093 [DSI2_RESET] = { 0x0210, 25 },
3094 [VFE_CSI_RESET] = { 0x0210, 24 },
3095 [MDP_RESET] = { 0x0210, 21 },
3096 [AMP_RESET] = { 0x0210, 20 },
3097 [JPEGD_RESET] = { 0x0210, 19 },
3098 [CSI1_RESET] = { 0x0210, 18 },
3099 [VPE_RESET] = { 0x0210, 17 },
3100 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
3101 [VFE_RESET] = { 0x0210, 15 },
3102 [GFX3D_RESET] = { 0x0210, 12 },
3103 [HDMI_RESET] = { 0x0210, 11 },
3104 [MMSS_IMEM_RESET] = { 0x0210, 10 },
3105 [IJPEG_RESET] = { 0x0210, 9 },
3106 [CSI0_RESET] = { 0x0210, 8 },
3107 [DSI_RESET] = { 0x0210, 7 },
3108 [VCODEC_RESET] = { 0x0210, 6 },
3109 [MDP_TV_RESET] = { 0x0210, 4 },
3110 [MDP_VSYNC_RESET] = { 0x0210, 3 },
3111 [ROT_RESET] = { 0x0210, 2 },
3112 [TV_HDMI_RESET] = { 0x0210, 1 },
3113 [VCAP_NPL_RESET] = { 0x0214, 4 },
3114 [VCAP_RESET] = { 0x0214, 3 },
3115 [CSI2_RESET] = { 0x0214, 2 },
3116 [CSI_RDI1_RESET] = { 0x0214, 1 },
3117 [CSI_RDI2_RESET] = { 0x0214 },
3124 .max_register = 0x334,
3132 .max_register = 0x350,
3168 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map; in mmcc_msm8960_probe()