Lines Matching +full:0 +full:x23000
33 { 249600000, 2000000000, 0 },
38 .l = 0x20,
39 .alpha = 0x0,
40 .config_ctl_val = 0x20485699,
41 .config_ctl_hi_val = 0x00002261,
42 .config_ctl_hi1_val = 0xB2923BBC,
43 .user_ctl_val = 0x00005100,
44 .user_ctl_hi_val = 0x00050805,
45 .user_ctl_hi1_val = 0x00000000,
49 .offset = 0x1000,
57 .index = 0,
66 { 0x5, 5 },
71 .offset = 0x1000,
89 .reg = 0x1054,
90 .shift = 0,
105 { P_BI_TCXO, 0 },
110 { .index = 0 },
115 { P_BI_TCXO, 0 },
127 F(19200000, P_BI_TCXO, 1, 0, 0),
128 F(51200000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 6, 0, 0),
129 F(102400000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 3, 0, 0),
130 F(204800000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 3, 0, 0),
135 .cmd_rcgr = 0x1d000,
158 F(8192000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 0, 0),
159 F(9600000, P_BI_TCXO, 2, 0, 0),
160 F(12288000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 0, 0),
161 F(19200000, P_BI_TCXO, 1, 0, 0),
162 F(24576000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5, 0, 0),
167 .cmd_rcgr = 0x10000,
181 .cmd_rcgr = 0x11000,
195 .cmd_rcgr = 0x20000,
209 .halt_reg = 0x1f000,
211 .hwcg_reg = 0x1f000,
214 .enable_reg = 0x1f000,
215 .enable_mask = BIT(0),
229 .halt_reg = 0x10018,
232 .enable_reg = 0x10018,
233 .enable_mask = BIT(0),
247 .halt_reg = 0x11018,
250 .enable_reg = 0x11018,
251 .enable_mask = BIT(0),
265 .halt_reg = 0x1e000,
268 .enable_reg = 0x1e000,
269 .enable_mask = BIT(0),
283 .halt_reg = 0x1e004,
286 .enable_reg = 0x1e004,
287 .enable_mask = BIT(0),
301 .halt_reg = 0x20014,
304 .enable_reg = 0x20014,
305 .enable_mask = BIT(0),
319 .halt_reg = 0x23000,
321 .hwcg_reg = 0x23000,
324 .enable_reg = 0x23000,
325 .enable_mask = BIT(0),
339 .gdscr = 0x0,
400 lpass_core_cc_sc7280_regmap_config.max_register = 0x4f004; in lpass_core_cc_sc7280_probe()
425 lpass_core_cc_sc7280_regmap_config.max_register = 0x24; in lpass_hm_core_probe()
428 return qcom_cc_probe_by_index(pdev, 0, desc); in lpass_hm_core_probe()