1 // SPDX-License-Identifier: GPL-2.0-only
7  * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8  * and supplies fixed rate clocks as output to the networking hardware
15  * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
19  *               +---------+
21  *               +--+---+--+
24  *          +-------+---+------+
25  *          |                  +-------------> eth0-50mhz
27  * -------->+                  +-------------> eth1-50mhz
29  *          |                  +-------------> eth2-50mhz
31  *          +----+----+----+---+-------------> eth-25mhz
38 #include <linux/clk-provider.h>
48 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
71  * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information
74  * @rate: Clock rate
79 	unsigned long rate;  member
83  * struct clk_cmn_pll - CMN PLL hardware specific data
85  * @hw: handle between common and hardware-specific interfaces
95 	.rate =		_rate,				\
109 	CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
110 	CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
111 	CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
112 	CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
113 	CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
114 	CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
115 	CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
116 	CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
117 	CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
121  * CMN PLL has the single parent clock, which supports the several
122  * possible parent clock rates, each parent clock rate is reflected
127 	int index = -EINVAL;  in ipq_cmn_pll_find_freq_index()
142 		 * Parent clock rate 48 MHZ and 96 MHZ take the same value  in ipq_cmn_pll_find_freq_index()
166 	 * by HW according to the parent clock rate.  in clk_cmn_pll_recalc_rate()
168 	regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);  in clk_cmn_pll_recalc_rate()
179 	/* Validate the rate of the single parent clock. */  in clk_cmn_pll_determine_rate()
180 	ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate);  in clk_cmn_pll_determine_rate()
186  * This function is used to initialize the CMN PLL to enable the fixed
187  * rate output clocks. It is expected to be configured once.
189 static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate,  in clk_cmn_pll_set_rate()  argument
198 	 * parent clock. The output clock rates are always of fixed value.  in clk_cmn_pll_set_rate()
204 	ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG,  in clk_cmn_pll_set_rate()
211 	 * Update the source clock rate selection and source clock  in clk_cmn_pll_set_rate()
212 	 * divider as 2 when the parent clock rate is 96 MHZ.  in clk_cmn_pll_set_rate()
215 		ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG,  in clk_cmn_pll_set_rate()
221 		ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION,  in clk_cmn_pll_set_rate()
229 	ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL,  in clk_cmn_pll_set_rate()
238 	ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,  in clk_cmn_pll_set_rate()
244 	ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,  in clk_cmn_pll_set_rate()
250 	return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val,  in clk_cmn_pll_set_rate()
264 	struct device *dev = &pdev->dev;  in ipq_cmn_pll_clk_hw_register()
281 		return ERR_PTR(-ENOMEM);  in ipq_cmn_pll_clk_hw_register()
288 	cmn_pll->hw.init = &init;  in ipq_cmn_pll_clk_hw_register()
289 	cmn_pll->regmap = regmap;  in ipq_cmn_pll_clk_hw_register()
291 	ret = devm_clk_hw_register(dev, &cmn_pll->hw);  in ipq_cmn_pll_clk_hw_register()
295 	return &cmn_pll->hw;  in ipq_cmn_pll_clk_hw_register()
302 	struct device *dev = &pdev->dev;  in ipq_cmn_pll_register_clks()
314 		return -ENOMEM;  in ipq_cmn_pll_register_clks()
317 	 * Register the CMN PLL clock, which is the parent clock of  in ipq_cmn_pll_register_clks()
318 	 * the fixed rate output clocks.  in ipq_cmn_pll_register_clks()
324 	/* Register the fixed rate output clocks. */  in ipq_cmn_pll_register_clks()
328 							  fixed_clk[i].rate);  in ipq_cmn_pll_register_clks()
334 		hw_data->hws[fixed_clk[i].id] = hw;  in ipq_cmn_pll_register_clks()
338 	 * Provide the CMN PLL clock. The clock rate of CMN PLL  in ipq_cmn_pll_register_clks()
339 	 * is configured to 12 GHZ by DT property assigned-clock-rates-u64.  in ipq_cmn_pll_register_clks()
341 	hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw;  in ipq_cmn_pll_register_clks()
342 	hw_data->num = num_clks + 1;  in ipq_cmn_pll_register_clks()
354 		clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]);  in ipq_cmn_pll_register_clks()
361 	struct device *dev = &pdev->dev;  in ipq_cmn_pll_clk_probe()
388 	/* Register CMN PLL clock and fixed rate output clocks. */  in ipq_cmn_pll_clk_probe()
407 	for (i = 0; i < hw_data->num; i++) {  in ipq_cmn_pll_clk_remove()
409 			clk_hw_unregister(hw_data->hws[i]);  in ipq_cmn_pll_clk_remove()
418 	{ .compatible = "qcom,ipq9574-cmn-pll", },