Lines Matching full:cmn

7  * CMN PLL block expects the reference clock from on-board Wi-Fi block,
14  * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
28  *          |  CMN PLL block   |
48 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
71  * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information
83  * struct clk_cmn_pll - CMN PLL hardware specific data
121  * CMN PLL has the single parent clock, which supports the several
186  * This function is used to initialize the CMN PLL to enable the fixed
235 	 * Reset the CMN PLL block to ensure the updated configurations  in clk_cmn_pll_set_rate()
249 	/* Stability check of CMN PLL output clocks. */  in clk_cmn_pll_set_rate()
317 	 * Register the CMN PLL clock, which is the parent clock of  in ipq_cmn_pll_register_clks()
338 	 * Provide the CMN PLL clock. The clock rate of CMN PLL  in ipq_cmn_pll_register_clks()
373 	 * To access the CMN PLL registers, the GCC AHB & SYS clocks  in ipq_cmn_pll_clk_probe()
374 	 * of CMN PLL block need to be enabled.  in ipq_cmn_pll_clk_probe()
388 	/* Register CMN PLL clock and fixed rate output clocks. */  in ipq_cmn_pll_clk_probe()
393 				     "Fail to register CMN PLL clocks\n");  in ipq_cmn_pll_clk_probe()
418 	{ .compatible = "qcom,ipq9574-cmn-pll", },
434 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver");