Lines Matching +full:100 +full:mhz
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
17 * with 31.25 MHZ.
25 * | +-------------> eth0-50mhz
27 * -------->+ +-------------> eth1-50mhz
29 * | +-------------> eth2-50mhz
31 * +----+----+----+---+-------------> eth-25mhz
109 CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
112 CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
113 CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
114 CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
115 CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
116 CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
117 CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
142 * Parent clock rate 48 MHZ and 96 MHZ take the same value in ipq_cmn_pll_find_freq_index()
143 * of reference clock index. 96 MHZ needs the source clock in ipq_cmn_pll_find_freq_index()
212 * divider as 2 when the parent clock rate is 96 MHZ. in clk_cmn_pll_set_rate()
252 100, 100 * USEC_PER_MSEC); in clk_cmn_pll_set_rate()