Lines Matching +full:0 +full:x32000
54 .offset = 0x0,
57 .enable_reg = 0x52020,
58 .enable_mask = BIT(0),
71 { 0x1, 2 },
76 .offset = 0x0,
93 .offset = 0x1000,
96 .enable_reg = 0x52020,
110 .offset = 0x4000,
113 .enable_reg = 0x52020,
127 .offset = 0x7000,
130 .enable_reg = 0x52020,
144 .offset = 0x9000,
147 .enable_reg = 0x52020,
161 { P_BI_TCXO, 0 },
173 { P_BI_TCXO, 0 },
187 { P_BI_TCXO, 0 },
203 { P_BI_TCXO, 0 },
217 { P_BI_TCXO, 0 },
227 { P_BI_TCXO, 0 },
241 { P_BI_TCXO, 0 },
249 { P_BI_TCXO, 0 },
265 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
275 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
285 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
295 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
305 .reg = 0x6b080,
319 .reg = 0x77068,
320 .shift = 0,
334 .reg = 0x770ec,
335 .shift = 0,
349 .reg = 0x77058,
350 .shift = 0,
364 .reg = 0x39070,
365 .shift = 0,
379 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
380 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
381 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
386 .cmd_rcgr = 0x64004,
401 .cmd_rcgr = 0x65004,
416 .cmd_rcgr = 0x66004,
431 F(19200000, P_BI_TCXO, 1, 0, 0),
436 .cmd_rcgr = 0x6b084,
451 F(19200000, P_BI_TCXO, 1, 0, 0),
452 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
457 .cmd_rcgr = 0x6b068,
458 .mnd_width = 0,
472 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
477 .cmd_rcgr = 0x33010,
478 .mnd_width = 0,
492 .cmd_rcgr = 0x17008,
493 .mnd_width = 0,
507 .cmd_rcgr = 0x17024,
508 .mnd_width = 0,
522 .cmd_rcgr = 0x17040,
523 .mnd_width = 0,
537 .cmd_rcgr = 0x1705c,
538 .mnd_width = 0,
552 .cmd_rcgr = 0x17078,
553 .mnd_width = 0,
567 .cmd_rcgr = 0x17094,
568 .mnd_width = 0,
582 .cmd_rcgr = 0x170b0,
583 .mnd_width = 0,
597 .cmd_rcgr = 0x170cc,
598 .mnd_width = 0,
612 .cmd_rcgr = 0x170e8,
613 .mnd_width = 0,
627 .cmd_rcgr = 0x17104,
628 .mnd_width = 0,
645 F(19200000, P_BI_TCXO, 1, 0, 0),
651 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
654 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
658 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
659 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
660 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
673 .cmd_rcgr = 0x188c0,
684 F(19200000, P_BI_TCXO, 1, 0, 0),
690 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
693 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
697 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
710 .cmd_rcgr = 0x18014,
727 .cmd_rcgr = 0x18150,
738 F(19200000, P_BI_TCXO, 1, 0, 0),
744 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
747 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
760 .cmd_rcgr = 0x182a0,
777 .cmd_rcgr = 0x183dc,
794 .cmd_rcgr = 0x18518,
811 .cmd_rcgr = 0x18654,
828 .cmd_rcgr = 0x18790,
837 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
842 .cmd_rcgr = 0x1e9f4,
843 .mnd_width = 0,
865 .cmd_rcgr = 0x1e014,
882 .cmd_rcgr = 0x1e150,
899 .cmd_rcgr = 0x1e28c,
916 .cmd_rcgr = 0x1e3c8,
933 .cmd_rcgr = 0x1e504,
950 .cmd_rcgr = 0x1e640,
961 F(19200000, P_BI_TCXO, 1, 0, 0),
967 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
970 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
987 .cmd_rcgr = 0x1e77c,
1004 .cmd_rcgr = 0x1e8b8,
1014 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1015 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1016 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1017 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1022 .cmd_rcgr = 0x1401c,
1038 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1039 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1044 .cmd_rcgr = 0x1601c,
1059 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1060 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1061 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1062 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1067 .cmd_rcgr = 0x77034,
1082 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1083 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1084 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1089 .cmd_rcgr = 0x7708c,
1090 .mnd_width = 0,
1104 F(9600000, P_BI_TCXO, 2, 0, 0),
1105 F(19200000, P_BI_TCXO, 1, 0, 0),
1110 .cmd_rcgr = 0x770c0,
1111 .mnd_width = 0,
1125 .cmd_rcgr = 0x770a4,
1126 .mnd_width = 0,
1140 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1141 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1142 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1143 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1148 .cmd_rcgr = 0x39030,
1163 .cmd_rcgr = 0x39048,
1164 .mnd_width = 0,
1178 .cmd_rcgr = 0x39074,
1179 .mnd_width = 0,
1193 .reg = 0x1828c,
1194 .shift = 0,
1208 .reg = 0x39060,
1209 .shift = 0,
1223 .halt_reg = 0x10068,
1225 .hwcg_reg = 0x10068,
1228 .enable_reg = 0x52000,
1238 .halt_reg = 0x770f0,
1240 .hwcg_reg = 0x770f0,
1243 .enable_reg = 0x770f0,
1244 .enable_mask = BIT(0),
1258 .halt_reg = 0x39090,
1260 .hwcg_reg = 0x39090,
1263 .enable_reg = 0x39090,
1264 .enable_mask = BIT(0),
1278 .halt_reg = 0x38004,
1280 .hwcg_reg = 0x38004,
1283 .enable_reg = 0x52000,
1293 .halt_reg = 0x26014,
1295 .hwcg_reg = 0x26014,
1298 .enable_reg = 0x26014,
1299 .enable_mask = BIT(0),
1308 .halt_reg = 0x26024,
1310 .hwcg_reg = 0x26024,
1313 .enable_reg = 0x26024,
1314 .enable_mask = BIT(0),
1323 .halt_reg = 0x10050,
1325 .hwcg_reg = 0x10050,
1328 .enable_reg = 0x52000,
1338 .halt_reg = 0x3908c,
1340 .hwcg_reg = 0x3908c,
1343 .enable_reg = 0x3908c,
1344 .enable_mask = BIT(0),
1358 .halt_reg = 0x10058,
1360 .hwcg_reg = 0x10058,
1363 .enable_reg = 0x52008,
1373 .halt_reg = 0x71150,
1375 .hwcg_reg = 0x71150,
1378 .enable_reg = 0x71150,
1379 .enable_mask = BIT(0),
1388 .halt_reg = 0x1007c,
1390 .hwcg_reg = 0x1007c,
1393 .enable_reg = 0x52000,
1403 .halt_reg = 0x27008,
1406 .enable_reg = 0x27008,
1407 .enable_mask = BIT(0),
1416 .halt_reg = 0x9f008,
1418 .hwcg_reg = 0x9f008,
1421 .enable_reg = 0x9f008,
1422 .enable_mask = BIT(0),
1431 .halt_reg = 0x9f018,
1433 .hwcg_reg = 0x9f018,
1436 .enable_reg = 0x9f018,
1437 .enable_mask = BIT(0),
1446 .halt_reg = 0x64000,
1449 .enable_reg = 0x64000,
1450 .enable_mask = BIT(0),
1464 .halt_reg = 0x65000,
1467 .enable_reg = 0x65000,
1468 .enable_mask = BIT(0),
1482 .halt_reg = 0x66000,
1485 .enable_reg = 0x66000,
1486 .enable_mask = BIT(0),
1500 .halt_reg = 0x71010,
1502 .hwcg_reg = 0x71010,
1505 .enable_reg = 0x71010,
1506 .enable_mask = BIT(0),
1517 .enable_reg = 0x52000,
1534 .enable_reg = 0x52000,
1549 .halt_reg = 0x6b044,
1552 .enable_reg = 0x52008,
1567 .halt_reg = 0x6b040,
1569 .hwcg_reg = 0x6b040,
1572 .enable_reg = 0x52008,
1582 .halt_reg = 0x6b030,
1584 .hwcg_reg = 0x6b030,
1587 .enable_reg = 0x52008,
1597 .halt_reg = 0x6b064,
1600 .enable_reg = 0x52000,
1615 .halt_reg = 0x6b054,
1618 .enable_reg = 0x52008,
1633 .halt_reg = 0x6b020,
1635 .hwcg_reg = 0x6b020,
1638 .enable_reg = 0x52008,
1639 .enable_mask = BIT(0),
1648 .halt_reg = 0x6b01c,
1651 .enable_reg = 0x52008,
1661 .halt_reg = 0x3300c,
1664 .enable_reg = 0x3300c,
1665 .enable_mask = BIT(0),
1679 .halt_reg = 0x33004,
1681 .hwcg_reg = 0x33004,
1684 .enable_reg = 0x33004,
1685 .enable_mask = BIT(0),
1694 .halt_reg = 0x33008,
1697 .enable_reg = 0x33008,
1698 .enable_mask = BIT(0),
1707 .halt_reg = 0x26010,
1709 .hwcg_reg = 0x26010,
1712 .enable_reg = 0x26010,
1713 .enable_mask = BIT(0),
1722 .halt_reg = 0x26008,
1724 .hwcg_reg = 0x26008,
1727 .enable_reg = 0x26008,
1728 .enable_mask = BIT(0),
1737 .halt_reg = 0x2600c,
1739 .hwcg_reg = 0x2600c,
1742 .enable_reg = 0x2600c,
1743 .enable_mask = BIT(0),
1752 .halt_reg = 0x71008,
1754 .hwcg_reg = 0x71008,
1757 .enable_reg = 0x71008,
1758 .enable_mask = BIT(0),
1767 .halt_reg = 0x6b018,
1769 .hwcg_reg = 0x6b018,
1772 .enable_reg = 0x52000,
1782 .halt_reg = 0x32014,
1784 .hwcg_reg = 0x32014,
1787 .enable_reg = 0x32014,
1788 .enable_mask = BIT(0),
1797 .halt_reg = 0x32008,
1799 .hwcg_reg = 0x32008,
1802 .enable_reg = 0x32008,
1803 .enable_mask = BIT(0),
1812 .halt_reg = 0x32010,
1814 .hwcg_reg = 0x32010,
1817 .enable_reg = 0x32010,
1818 .enable_mask = BIT(0),
1827 .halt_reg = 0x3200c,
1829 .hwcg_reg = 0x3200c,
1832 .enable_reg = 0x3200c,
1833 .enable_mask = BIT(0),
1842 .halt_reg = 0x23004,
1845 .enable_reg = 0x52008,
1855 .halt_reg = 0x17004,
1858 .enable_reg = 0x52008,
1873 .halt_reg = 0x17020,
1876 .enable_reg = 0x52008,
1891 .halt_reg = 0x1703c,
1894 .enable_reg = 0x52008,
1909 .halt_reg = 0x17058,
1912 .enable_reg = 0x52008,
1927 .halt_reg = 0x17074,
1930 .enable_reg = 0x52008,
1945 .halt_reg = 0x17090,
1948 .enable_reg = 0x52008,
1963 .halt_reg = 0x170ac,
1966 .enable_reg = 0x52008,
1981 .halt_reg = 0x170c8,
1984 .enable_reg = 0x52008,
1999 .halt_reg = 0x170e4,
2002 .enable_reg = 0x52010,
2017 .halt_reg = 0x17100,
2020 .enable_reg = 0x52010,
2035 .halt_reg = 0x23000,
2037 .hwcg_reg = 0x23000,
2040 .enable_reg = 0x52008,
2050 .halt_reg = 0x2315c,
2053 .enable_reg = 0x52008,
2063 .halt_reg = 0x23148,
2066 .enable_reg = 0x52008,
2076 .halt_reg = 0x188bc,
2079 .enable_reg = 0x52010,
2094 .halt_reg = 0x18004,
2097 .enable_reg = 0x52008,
2112 .halt_reg = 0x18140,
2115 .enable_reg = 0x52008,
2130 .halt_reg = 0x1827c,
2133 .enable_reg = 0x52008,
2148 .halt_reg = 0x18290,
2151 .enable_reg = 0x52008,
2166 .halt_reg = 0x183cc,
2169 .enable_reg = 0x52008,
2184 .halt_reg = 0x18508,
2187 .enable_reg = 0x52008,
2202 .halt_reg = 0x18644,
2205 .enable_reg = 0x52008,
2220 .halt_reg = 0x18780,
2223 .enable_reg = 0x52010,
2238 .halt_reg = 0x232b4,
2241 .enable_reg = 0x52010,
2251 .halt_reg = 0x232a0,
2254 .enable_reg = 0x52010,
2255 .enable_mask = BIT(0),
2264 .halt_reg = 0x1e9ec,
2266 .hwcg_reg = 0x1e9ec,
2269 .enable_reg = 0x52010,
2284 .halt_reg = 0x1e9f0,
2286 .hwcg_reg = 0x1e9f0,
2289 .enable_reg = 0x52010,
2304 .halt_reg = 0x1e004,
2307 .enable_reg = 0x52010,
2322 .halt_reg = 0x1e140,
2325 .enable_reg = 0x52010,
2340 .halt_reg = 0x1e27c,
2343 .enable_reg = 0x52010,
2358 .halt_reg = 0x1e3b8,
2361 .enable_reg = 0x52010,
2376 .halt_reg = 0x1e4f4,
2379 .enable_reg = 0x52010,
2394 .halt_reg = 0x1e630,
2397 .enable_reg = 0x52010,
2412 .halt_reg = 0x1e76c,
2415 .enable_reg = 0x52010,
2430 .halt_reg = 0x1e8a8,
2433 .enable_reg = 0x52010,
2448 .halt_reg = 0x23140,
2450 .hwcg_reg = 0x23140,
2453 .enable_reg = 0x52008,
2463 .halt_reg = 0x23144,
2465 .hwcg_reg = 0x23144,
2468 .enable_reg = 0x52008,
2478 .halt_reg = 0x1e9e4,
2480 .hwcg_reg = 0x1e9e4,
2483 .enable_reg = 0x52010,
2493 .halt_reg = 0x1e9e8,
2495 .hwcg_reg = 0x1e9e8,
2498 .enable_reg = 0x52010,
2508 .halt_reg = 0x23298,
2510 .hwcg_reg = 0x23298,
2513 .enable_reg = 0x52010,
2523 .halt_reg = 0x2329c,
2525 .hwcg_reg = 0x2329c,
2528 .enable_reg = 0x52010,
2538 .halt_reg = 0x14014,
2541 .enable_reg = 0x14014,
2542 .enable_mask = BIT(0),
2551 .halt_reg = 0x14004,
2554 .enable_reg = 0x14004,
2555 .enable_mask = BIT(0),
2569 .halt_reg = 0x16014,
2572 .enable_reg = 0x16014,
2573 .enable_mask = BIT(0),
2582 .halt_reg = 0x16004,
2585 .enable_reg = 0x16004,
2586 .enable_mask = BIT(0),
2600 .halt_reg = 0x77028,
2602 .hwcg_reg = 0x77028,
2605 .enable_reg = 0x77028,
2606 .enable_mask = BIT(0),
2615 .halt_reg = 0x77018,
2617 .hwcg_reg = 0x77018,
2620 .enable_reg = 0x77018,
2621 .enable_mask = BIT(0),
2635 .halt_reg = 0x7707c,
2637 .hwcg_reg = 0x7707c,
2640 .enable_reg = 0x7707c,
2641 .enable_mask = BIT(0),
2655 .halt_reg = 0x770bc,
2657 .hwcg_reg = 0x770bc,
2660 .enable_reg = 0x770bc,
2661 .enable_mask = BIT(0),
2675 .halt_reg = 0x77030,
2678 .enable_reg = 0x77030,
2679 .enable_mask = BIT(0),
2693 .halt_reg = 0x770d8,
2696 .enable_reg = 0x770d8,
2697 .enable_mask = BIT(0),
2711 .halt_reg = 0x7702c,
2714 .enable_reg = 0x7702c,
2715 .enable_mask = BIT(0),
2729 .halt_reg = 0x7706c,
2731 .hwcg_reg = 0x7706c,
2734 .enable_reg = 0x7706c,
2735 .enable_mask = BIT(0),
2749 .halt_reg = 0x39018,
2752 .enable_reg = 0x39018,
2753 .enable_mask = BIT(0),
2767 .halt_reg = 0x3902c,
2770 .enable_reg = 0x3902c,
2771 .enable_mask = BIT(0),
2785 .halt_reg = 0x39028,
2788 .enable_reg = 0x39028,
2789 .enable_mask = BIT(0),
2798 .halt_reg = 0x39064,
2801 .enable_reg = 0x39064,
2802 .enable_mask = BIT(0),
2816 .halt_reg = 0x39068,
2819 .enable_reg = 0x39068,
2820 .enable_mask = BIT(0),
2834 .halt_reg = 0x3906c,
2836 .hwcg_reg = 0x3906c,
2839 .enable_reg = 0x3906c,
2840 .enable_mask = BIT(0),
2854 .halt_reg = 0x32018,
2856 .hwcg_reg = 0x32018,
2859 .enable_reg = 0x32018,
2860 .enable_mask = BIT(0),
2869 .halt_reg = 0x32028,
2871 .hwcg_reg = 0x32028,
2874 .enable_reg = 0x32028,
2875 .enable_mask = BIT(0),
2884 .gdscr = 0x6b004,
2885 .en_rest_wait_val = 0x2,
2886 .en_few_wait_val = 0x2,
2887 .clk_dis_wait_val = 0xf,
2888 .collapse_ctrl = 0x5214c,
2889 .collapse_mask = BIT(0),
2898 .gdscr = 0x6c000,
2899 .en_rest_wait_val = 0x2,
2900 .en_few_wait_val = 0x2,
2901 .clk_dis_wait_val = 0x2,
2902 .collapse_ctrl = 0x5214c,
2912 .gdscr = 0x9e000,
2913 .en_rest_wait_val = 0x2,
2914 .en_few_wait_val = 0x2,
2915 .clk_dis_wait_val = 0x2,
2924 .gdscr = 0x77004,
2925 .en_rest_wait_val = 0x2,
2926 .en_few_wait_val = 0x2,
2927 .clk_dis_wait_val = 0xf,
2936 .gdscr = 0x39004,
2937 .en_rest_wait_val = 0x2,
2938 .en_few_wait_val = 0x2,
2939 .clk_dis_wait_val = 0xf,
2948 .gdscr = 0x50018,
2949 .en_rest_wait_val = 0x2,
2950 .en_few_wait_val = 0x2,
2951 .clk_dis_wait_val = 0x2,
3127 [GCC_CAMERA_BCR] = { 0x26000 },
3128 [GCC_DISPLAY_BCR] = { 0x27000 },
3129 [GCC_EVA_BCR] = { 0x9f000 },
3130 [GCC_EVA_AXI0_CLK_ARES] = { 0x9f008, 2 },
3131 [GCC_EVA_AXI0C_CLK_ARES] = { 0x9f018, 2 },
3132 [GCC_GPU_BCR] = { 0x71000 },
3133 [GCC_PCIE_0_BCR] = { 0x6b000 },
3134 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3135 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3136 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3137 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3138 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3139 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3140 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3141 [GCC_PCIE_RSCC_BCR] = { 0x11000 },
3142 [GCC_PDM_BCR] = { 0x33000 },
3143 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3144 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3145 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
3146 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3147 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3148 [GCC_SDCC2_BCR] = { 0x14000 },
3149 [GCC_SDCC4_BCR] = { 0x16000 },
3150 [GCC_UFS_PHY_BCR] = { 0x77000 },
3151 [GCC_USB30_PRIM_BCR] = { 0x39000 },
3152 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3153 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3154 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3155 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3156 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3157 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3158 [GCC_VIDEO_BCR] = { 0x32000 },
3159 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
3160 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32028, 2 },
3187 .max_register = 0x1f41f0,
3235 qcom_branch_set_clk_en(regmap, 0xa0004); in gcc_sm8750_probe()
3236 qcom_branch_set_clk_en(regmap, 0x26004); in gcc_sm8750_probe()
3237 qcom_branch_set_clk_en(regmap, 0x26034); in gcc_sm8750_probe()
3238 qcom_branch_set_clk_en(regmap, 0x27004); in gcc_sm8750_probe()
3239 qcom_branch_set_clk_en(regmap, 0x9f004); in gcc_sm8750_probe()
3240 qcom_branch_set_clk_en(regmap, 0x9f01c); in gcc_sm8750_probe()
3241 qcom_branch_set_clk_en(regmap, 0x71004); in gcc_sm8750_probe()
3242 qcom_branch_set_clk_en(regmap, 0x32004); in gcc_sm8750_probe()
3243 qcom_branch_set_clk_en(regmap, 0x32038); in gcc_sm8750_probe()
3244 regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); in gcc_sm8750_probe()
3245 regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); in gcc_sm8750_probe()