Lines Matching +full:0 +full:x33000
36 .offset = 0x0,
39 .enable_reg = 0x52000,
40 .enable_mask = BIT(0),
54 { 0x0, 1 },
55 { 0x1, 2 },
56 { 0x3, 4 },
57 { 0x7, 8 },
62 .offset = 0x0,
79 .offset = 0x1a000,
82 .enable_reg = 0x52000,
97 .offset = 0x1c000,
100 .enable_reg = 0x52000,
115 { P_BI_TCXO, 0 },
127 { P_BI_TCXO, 0 },
141 { P_BI_TCXO, 0 },
151 { P_BI_TCXO, 0 },
161 { P_BI_TCXO, 0 },
169 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
197 { P_BI_TCXO, 0 },
211 F(19200000, P_BI_TCXO, 1, 0, 0),
212 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
213 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
214 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
219 .cmd_rcgr = 0x6038,
220 .mnd_width = 0,
236 F(19200000, P_BI_TCXO, 1, 0, 0),
237 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
238 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
239 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
240 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
245 .cmd_rcgr = 0x601c,
260 F(19200000, P_BI_TCXO, 1, 0, 0),
261 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
262 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
263 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
264 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
269 .cmd_rcgr = 0x64004,
284 .cmd_rcgr = 0x65004,
299 .cmd_rcgr = 0x66004,
314 F(9600000, P_BI_TCXO, 2, 0, 0),
315 F(19200000, P_BI_TCXO, 1, 0, 0),
320 .cmd_rcgr = 0x6b02c,
335 .cmd_rcgr = 0x8d02c,
350 F(19200000, P_BI_TCXO, 1, 0, 0),
351 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
356 .cmd_rcgr = 0x6f014,
357 .mnd_width = 0,
371 F(9600000, P_BI_TCXO, 2, 0, 0),
372 F(19200000, P_BI_TCXO, 1, 0, 0),
373 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
378 .cmd_rcgr = 0x33010,
379 .mnd_width = 0,
393 F(19200000, P_BI_TCXO, 1, 0, 0),
394 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
395 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
396 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
401 .cmd_rcgr = 0x4b008,
402 .mnd_width = 0,
418 F(19200000, P_BI_TCXO, 1, 0, 0),
425 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
429 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
443 .cmd_rcgr = 0x17148,
460 .cmd_rcgr = 0x17278,
477 .cmd_rcgr = 0x173a8,
494 .cmd_rcgr = 0x174d8,
511 .cmd_rcgr = 0x17608,
528 .cmd_rcgr = 0x17738,
545 .cmd_rcgr = 0x17868,
562 .cmd_rcgr = 0x17998,
579 .cmd_rcgr = 0x18148,
596 .cmd_rcgr = 0x18278,
613 .cmd_rcgr = 0x183a8,
630 .cmd_rcgr = 0x184d8,
647 .cmd_rcgr = 0x18608,
664 .cmd_rcgr = 0x18738,
681 .cmd_rcgr = 0x1e148,
698 .cmd_rcgr = 0x1e278,
715 .cmd_rcgr = 0x1e3a8,
732 .cmd_rcgr = 0x1e4d8,
749 .cmd_rcgr = 0x1e608,
766 .cmd_rcgr = 0x1e738,
776 F(9600000, P_BI_TCXO, 2, 0, 0),
777 F(19200000, P_BI_TCXO, 1, 0, 0),
779 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
780 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
781 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
786 .cmd_rcgr = 0x1400c,
802 F(9600000, P_BI_TCXO, 2, 0, 0),
803 F(19200000, P_BI_TCXO, 1, 0, 0),
805 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
806 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
811 .cmd_rcgr = 0x1600c,
831 .cmd_rcgr = 0x36010,
846 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
847 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
848 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
849 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
850 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
855 .cmd_rcgr = 0x75020,
870 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
871 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
872 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
873 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
878 .cmd_rcgr = 0x75060,
879 .mnd_width = 0,
893 F(19200000, P_BI_TCXO, 1, 0, 0),
898 .cmd_rcgr = 0x75094,
899 .mnd_width = 0,
913 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
914 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
915 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
920 .cmd_rcgr = 0x75078,
921 .mnd_width = 0,
935 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
936 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
937 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
938 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
939 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
944 .cmd_rcgr = 0x77020,
959 .cmd_rcgr = 0x77060,
960 .mnd_width = 0,
974 .cmd_rcgr = 0x77094,
975 .mnd_width = 0,
989 .cmd_rcgr = 0x77078,
990 .mnd_width = 0,
1004 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1005 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1006 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1007 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1008 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1013 .cmd_rcgr = 0xf01c,
1028 F(19200000, P_BI_TCXO, 1, 0, 0),
1029 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1030 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1035 .cmd_rcgr = 0xf034,
1036 .mnd_width = 0,
1050 .cmd_rcgr = 0x1001c,
1065 .cmd_rcgr = 0x10034,
1066 .mnd_width = 0,
1080 .cmd_rcgr = 0xf060,
1081 .mnd_width = 0,
1095 .cmd_rcgr = 0x10060,
1096 .mnd_width = 0,
1110 .halt_reg = 0x90018,
1113 .enable_reg = 0x90018,
1114 .enable_mask = BIT(0),
1123 .halt_reg = 0x750c0,
1125 .hwcg_reg = 0x750c0,
1128 .enable_reg = 0x750c0,
1129 .enable_mask = BIT(0),
1142 .halt_reg = 0x750c0,
1144 .hwcg_reg = 0x750c0,
1147 .enable_reg = 0x750c0,
1161 .halt_reg = 0x770c0,
1163 .hwcg_reg = 0x770c0,
1166 .enable_reg = 0x770c0,
1167 .enable_mask = BIT(0),
1180 .halt_reg = 0x770c0,
1182 .hwcg_reg = 0x770c0,
1185 .enable_reg = 0x770c0,
1199 .halt_reg = 0xf07c,
1202 .enable_reg = 0xf07c,
1203 .enable_mask = BIT(0),
1216 .halt_reg = 0x1007c,
1219 .enable_reg = 0x1007c,
1220 .enable_mask = BIT(0),
1233 .halt_reg = 0x38004,
1235 .hwcg_reg = 0x38004,
1238 .enable_reg = 0x52004,
1252 .halt_reg = 0xb008,
1254 .hwcg_reg = 0xb008,
1257 .enable_reg = 0xb008,
1258 .enable_mask = BIT(0),
1268 .halt_reg = 0xb030,
1271 .enable_reg = 0xb030,
1272 .enable_mask = BIT(0),
1281 .halt_reg = 0xb034,
1284 .enable_reg = 0xb034,
1285 .enable_mask = BIT(0),
1295 .halt_reg = 0xb044,
1298 .enable_reg = 0xb044,
1299 .enable_mask = BIT(0),
1309 .halt_reg = 0xf078,
1312 .enable_reg = 0xf078,
1313 .enable_mask = BIT(0),
1326 .halt_reg = 0x10078,
1329 .enable_reg = 0x10078,
1330 .enable_mask = BIT(0),
1343 .halt_reg = 0x48190,
1346 .enable_reg = 0x48190,
1347 .enable_mask = BIT(0),
1358 .halt_reg = 0x48004,
1360 .hwcg_reg = 0x48004,
1363 .enable_reg = 0x52004,
1375 .halt_reg = 0x48008,
1378 .enable_reg = 0x48008,
1379 .enable_mask = BIT(0),
1388 .halt_reg = 0x71154,
1391 .enable_reg = 0x71154,
1392 .enable_mask = BIT(0),
1405 .halt_reg = 0xb00c,
1407 .hwcg_reg = 0xb00c,
1410 .enable_reg = 0xb00c,
1411 .enable_mask = BIT(0),
1421 .halt_reg = 0xb038,
1424 .enable_reg = 0xb038,
1425 .enable_mask = BIT(0),
1434 .halt_reg = 0xb03c,
1437 .enable_reg = 0xb03c,
1438 .enable_mask = BIT(0),
1448 .halt_reg = 0xb048,
1451 .enable_reg = 0xb048,
1452 .enable_mask = BIT(0),
1462 .halt_reg = 0x6010,
1465 .enable_reg = 0x6010,
1466 .enable_mask = BIT(0),
1475 .halt_reg = 0x6034,
1478 .enable_reg = 0x6034,
1479 .enable_mask = BIT(0),
1492 .halt_reg = 0x6018,
1495 .enable_reg = 0x6018,
1496 .enable_mask = BIT(0),
1509 .halt_reg = 0x6014,
1511 .hwcg_reg = 0x6014,
1514 .enable_reg = 0x6014,
1515 .enable_mask = BIT(0),
1524 .halt_reg = 0x64000,
1527 .enable_reg = 0x64000,
1528 .enable_mask = BIT(0),
1541 .halt_reg = 0x65000,
1544 .enable_reg = 0x65000,
1545 .enable_mask = BIT(0),
1558 .halt_reg = 0x66000,
1561 .enable_reg = 0x66000,
1562 .enable_mask = BIT(0),
1575 .halt_reg = 0x71004,
1577 .hwcg_reg = 0x71004,
1580 .enable_reg = 0x71004,
1581 .enable_mask = BIT(0),
1594 .enable_reg = 0x52004,
1610 .enable_reg = 0x52004,
1624 .halt_reg = 0x8c010,
1627 .enable_reg = 0x8c010,
1628 .enable_mask = BIT(0),
1637 .halt_reg = 0x7100c,
1640 .enable_reg = 0x7100c,
1641 .enable_mask = BIT(0),
1650 .halt_reg = 0x71018,
1653 .enable_reg = 0x71018,
1654 .enable_mask = BIT(0),
1663 .halt_reg = 0x4d010,
1666 .enable_reg = 0x4d010,
1667 .enable_mask = BIT(0),
1676 .halt_reg = 0x4d008,
1679 .enable_reg = 0x4d008,
1680 .enable_mask = BIT(0),
1689 .halt_reg = 0x4d004,
1691 .hwcg_reg = 0x4d004,
1694 .enable_reg = 0x4d004,
1695 .enable_mask = BIT(0),
1708 .enable_reg = 0x52004,
1724 .enable_reg = 0x52004,
1738 .halt_reg = 0x4d00c,
1741 .enable_reg = 0x4d00c,
1742 .enable_mask = BIT(0),
1751 .halt_reg = 0x6f02c,
1754 .enable_reg = 0x6f02c,
1755 .enable_mask = BIT(0),
1768 .halt_reg = 0x6f030,
1771 .enable_reg = 0x6f030,
1772 .enable_mask = BIT(0),
1785 .halt_reg = 0x6b020,
1788 .enable_reg = 0x5200c,
1802 .halt_reg = 0x6b01c,
1804 .hwcg_reg = 0x6b01c,
1807 .enable_reg = 0x5200c,
1817 .halt_reg = 0x8c00c,
1820 .enable_reg = 0x8c00c,
1821 .enable_mask = BIT(0),
1830 .halt_reg = 0x6b018,
1833 .enable_reg = 0x5200c,
1844 .halt_reg = 0x6b024,
1847 .enable_reg = 0x5200c,
1857 .halt_reg = 0x6b014,
1859 .hwcg_reg = 0x6b014,
1862 .enable_reg = 0x5200c,
1863 .enable_mask = BIT(0),
1872 .halt_reg = 0x6b010,
1875 .enable_reg = 0x5200c,
1885 .halt_reg = 0x8d020,
1888 .enable_reg = 0x52004,
1902 .halt_reg = 0x8d01c,
1904 .hwcg_reg = 0x8d01c,
1907 .enable_reg = 0x52004,
1917 .halt_reg = 0x8c02c,
1920 .enable_reg = 0x8c02c,
1921 .enable_mask = BIT(0),
1930 .halt_reg = 0x8d018,
1933 .enable_reg = 0x52004,
1944 .halt_reg = 0x8d024,
1947 .enable_reg = 0x52004,
1957 .halt_reg = 0x8d014,
1959 .hwcg_reg = 0x8d014,
1962 .enable_reg = 0x52004,
1972 .halt_reg = 0x8d010,
1975 .enable_reg = 0x52004,
1985 .halt_reg = 0x6f004,
1988 .enable_reg = 0x6f004,
1989 .enable_mask = BIT(0),
2002 .halt_reg = 0x3300c,
2005 .enable_reg = 0x3300c,
2006 .enable_mask = BIT(0),
2019 .halt_reg = 0x33004,
2021 .hwcg_reg = 0x33004,
2024 .enable_reg = 0x33004,
2025 .enable_mask = BIT(0),
2034 .halt_reg = 0x33008,
2037 .enable_reg = 0x33008,
2038 .enable_mask = BIT(0),
2047 .halt_reg = 0x34004,
2050 .enable_reg = 0x52004,
2060 .halt_reg = 0xb018,
2062 .hwcg_reg = 0xb018,
2065 .enable_reg = 0xb018,
2066 .enable_mask = BIT(0),
2075 .halt_reg = 0xb01c,
2077 .hwcg_reg = 0xb01c,
2080 .enable_reg = 0xb01c,
2081 .enable_mask = BIT(0),
2090 .halt_reg = 0xb020,
2092 .hwcg_reg = 0xb020,
2095 .enable_reg = 0xb020,
2096 .enable_mask = BIT(0),
2105 .halt_reg = 0xb010,
2107 .hwcg_reg = 0xb010,
2110 .enable_reg = 0xb010,
2111 .enable_mask = BIT(0),
2120 .halt_reg = 0xb014,
2122 .hwcg_reg = 0xb014,
2125 .enable_reg = 0xb014,
2126 .enable_mask = BIT(0),
2135 .halt_reg = 0x4b000,
2138 .enable_reg = 0x4b000,
2139 .enable_mask = BIT(0),
2148 .halt_reg = 0x4b004,
2151 .enable_reg = 0x4b004,
2152 .enable_mask = BIT(0),
2165 .halt_reg = 0x17144,
2168 .enable_reg = 0x5200c,
2182 .halt_reg = 0x17274,
2185 .enable_reg = 0x5200c,
2199 .halt_reg = 0x173a4,
2202 .enable_reg = 0x5200c,
2216 .halt_reg = 0x174d4,
2219 .enable_reg = 0x5200c,
2233 .halt_reg = 0x17604,
2236 .enable_reg = 0x5200c,
2250 .halt_reg = 0x17734,
2253 .enable_reg = 0x5200c,
2267 .halt_reg = 0x17864,
2270 .enable_reg = 0x5200c,
2284 .halt_reg = 0x17994,
2287 .enable_reg = 0x5200c,
2301 .halt_reg = 0x18144,
2304 .enable_reg = 0x5200c,
2318 .halt_reg = 0x18274,
2321 .enable_reg = 0x5200c,
2335 .halt_reg = 0x183a4,
2338 .enable_reg = 0x5200c,
2352 .halt_reg = 0x184d4,
2355 .enable_reg = 0x5200c,
2369 .halt_reg = 0x18604,
2372 .enable_reg = 0x5200c,
2386 .halt_reg = 0x18734,
2389 .enable_reg = 0x5200c,
2403 .halt_reg = 0x1e144,
2406 .enable_reg = 0x52014,
2420 .halt_reg = 0x1e274,
2423 .enable_reg = 0x52014,
2437 .halt_reg = 0x1e3a4,
2440 .enable_reg = 0x52014,
2454 .halt_reg = 0x1e4d4,
2457 .enable_reg = 0x52014,
2471 .halt_reg = 0x1e604,
2474 .enable_reg = 0x52014,
2488 .halt_reg = 0x1e734,
2491 .enable_reg = 0x52014,
2505 .halt_reg = 0x17004,
2508 .enable_reg = 0x5200c,
2518 .halt_reg = 0x17008,
2520 .hwcg_reg = 0x17008,
2523 .enable_reg = 0x5200c,
2533 .halt_reg = 0x18004,
2536 .enable_reg = 0x5200c,
2546 .halt_reg = 0x18008,
2548 .hwcg_reg = 0x18008,
2551 .enable_reg = 0x5200c,
2561 .halt_reg = 0x1e004,
2564 .enable_reg = 0x52014,
2574 .halt_reg = 0x1e008,
2576 .hwcg_reg = 0x1e008,
2579 .enable_reg = 0x52014,
2589 .halt_reg = 0x14008,
2592 .enable_reg = 0x14008,
2593 .enable_mask = BIT(0),
2602 .halt_reg = 0x14004,
2605 .enable_reg = 0x14004,
2606 .enable_mask = BIT(0),
2619 .halt_reg = 0x16008,
2622 .enable_reg = 0x16008,
2623 .enable_mask = BIT(0),
2632 .halt_reg = 0x16004,
2635 .enable_reg = 0x16004,
2636 .enable_mask = BIT(0),
2649 .halt_reg = 0x36004,
2652 .enable_reg = 0x36004,
2653 .enable_mask = BIT(0),
2662 .halt_reg = 0x3600c,
2665 .enable_reg = 0x3600c,
2666 .enable_mask = BIT(0),
2675 .halt_reg = 0x36008,
2678 .enable_reg = 0x36008,
2679 .enable_mask = BIT(0),
2692 .halt_reg = 0x75014,
2694 .hwcg_reg = 0x75014,
2697 .enable_reg = 0x75014,
2698 .enable_mask = BIT(0),
2707 .halt_reg = 0x75010,
2709 .hwcg_reg = 0x75010,
2712 .enable_reg = 0x75010,
2713 .enable_mask = BIT(0),
2726 .halt_reg = 0x75010,
2728 .hwcg_reg = 0x75010,
2731 .enable_reg = 0x75010,
2745 .halt_reg = 0x8c004,
2748 .enable_reg = 0x8c004,
2749 .enable_mask = BIT(0),
2758 .halt_reg = 0x7505c,
2760 .hwcg_reg = 0x7505c,
2763 .enable_reg = 0x7505c,
2764 .enable_mask = BIT(0),
2777 .halt_reg = 0x7505c,
2779 .hwcg_reg = 0x7505c,
2782 .enable_reg = 0x7505c,
2796 .halt_reg = 0x75090,
2798 .hwcg_reg = 0x75090,
2801 .enable_reg = 0x75090,
2802 .enable_mask = BIT(0),
2815 .halt_reg = 0x75090,
2817 .hwcg_reg = 0x75090,
2820 .enable_reg = 0x75090,
2837 .enable_reg = 0x7501c,
2838 .enable_mask = BIT(0),
2850 .enable_reg = 0x750ac,
2851 .enable_mask = BIT(0),
2863 .enable_reg = 0x75018,
2864 .enable_mask = BIT(0),
2873 .halt_reg = 0x75058,
2875 .hwcg_reg = 0x75058,
2878 .enable_reg = 0x75058,
2879 .enable_mask = BIT(0),
2892 .halt_reg = 0x75058,
2894 .hwcg_reg = 0x75058,
2897 .enable_reg = 0x75058,
2911 .halt_reg = 0x8c000,
2914 .enable_reg = 0x8c000,
2915 .enable_mask = BIT(0),
2924 .halt_reg = 0x77014,
2926 .hwcg_reg = 0x77014,
2929 .enable_reg = 0x77014,
2930 .enable_mask = BIT(0),
2939 .halt_reg = 0x77010,
2941 .hwcg_reg = 0x77010,
2944 .enable_reg = 0x77010,
2945 .enable_mask = BIT(0),
2958 .halt_reg = 0x77010,
2960 .hwcg_reg = 0x77010,
2963 .enable_reg = 0x77010,
2977 .halt_reg = 0x7705c,
2979 .hwcg_reg = 0x7705c,
2982 .enable_reg = 0x7705c,
2983 .enable_mask = BIT(0),
2996 .halt_reg = 0x7705c,
2998 .hwcg_reg = 0x7705c,
3001 .enable_reg = 0x7705c,
3015 .halt_reg = 0x77090,
3017 .hwcg_reg = 0x77090,
3020 .enable_reg = 0x77090,
3021 .enable_mask = BIT(0),
3034 .halt_reg = 0x77090,
3036 .hwcg_reg = 0x77090,
3039 .enable_reg = 0x77090,
3056 .enable_reg = 0x7701c,
3057 .enable_mask = BIT(0),
3069 .enable_reg = 0x770ac,
3070 .enable_mask = BIT(0),
3082 .enable_reg = 0x77018,
3083 .enable_mask = BIT(0),
3092 .halt_reg = 0x77058,
3094 .hwcg_reg = 0x77058,
3097 .enable_reg = 0x77058,
3098 .enable_mask = BIT(0),
3111 .halt_reg = 0x77058,
3113 .hwcg_reg = 0x77058,
3116 .enable_reg = 0x77058,
3130 .halt_reg = 0xf010,
3133 .enable_reg = 0xf010,
3134 .enable_mask = BIT(0),
3147 .halt_reg = 0xf018,
3150 .enable_reg = 0xf018,
3151 .enable_mask = BIT(0),
3164 .halt_reg = 0xf014,
3167 .enable_reg = 0xf014,
3168 .enable_mask = BIT(0),
3177 .halt_reg = 0x10010,
3180 .enable_reg = 0x10010,
3181 .enable_mask = BIT(0),
3194 .halt_reg = 0x10018,
3197 .enable_reg = 0x10018,
3198 .enable_mask = BIT(0),
3211 .halt_reg = 0x10014,
3214 .enable_reg = 0x10014,
3215 .enable_mask = BIT(0),
3224 .halt_reg = 0x8c008,
3227 .enable_reg = 0x8c008,
3228 .enable_mask = BIT(0),
3237 .halt_reg = 0xf050,
3240 .enable_reg = 0xf050,
3241 .enable_mask = BIT(0),
3254 .halt_reg = 0xf054,
3257 .enable_reg = 0xf054,
3258 .enable_mask = BIT(0),
3273 .enable_reg = 0xf058,
3274 .enable_mask = BIT(0),
3283 .halt_reg = 0x8c028,
3286 .enable_reg = 0x8c028,
3287 .enable_mask = BIT(0),
3296 .halt_reg = 0x10050,
3299 .enable_reg = 0x10050,
3300 .enable_mask = BIT(0),
3313 .halt_reg = 0x10054,
3316 .enable_reg = 0x10054,
3317 .enable_mask = BIT(0),
3332 .enable_reg = 0x10058,
3333 .enable_mask = BIT(0),
3346 .halt_reg = 0xb004,
3348 .hwcg_reg = 0xb004,
3351 .enable_reg = 0xb004,
3352 .enable_mask = BIT(0),
3362 .halt_reg = 0xb024,
3365 .enable_reg = 0xb024,
3366 .enable_mask = BIT(0),
3375 .halt_reg = 0xb028,
3378 .enable_reg = 0xb028,
3379 .enable_mask = BIT(0),
3388 .halt_reg = 0xb02c,
3391 .enable_reg = 0xb02c,
3392 .enable_mask = BIT(0),
3402 .halt_reg = 0xb040,
3405 .enable_reg = 0xb040,
3406 .enable_mask = BIT(0),
3416 .gdscr = 0x6b004,
3425 .gdscr = 0x8d004,
3434 .gdscr = 0x75004,
3443 .gdscr = 0x77004,
3452 .gdscr = 0x6004,
3461 .gdscr = 0xf004,
3470 .gdscr = 0x10004,
3691 [GCC_EMAC_BCR] = { 0x6000 },
3692 [GCC_GPU_BCR] = { 0x71000 },
3693 [GCC_MMSS_BCR] = { 0xb000 },
3694 [GCC_NPU_BCR] = { 0x4d000 },
3695 [GCC_PCIE_0_BCR] = { 0x6b000 },
3696 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3697 [GCC_PCIE_1_BCR] = { 0x8d000 },
3698 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3699 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3700 [GCC_PDM_BCR] = { 0x33000 },
3701 [GCC_PRNG_BCR] = { 0x34000 },
3702 [GCC_QSPI_BCR] = { 0x24008 },
3703 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3704 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3705 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3706 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3707 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3708 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3709 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3710 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3711 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3712 [GCC_SDCC2_BCR] = { 0x14000 },
3713 [GCC_SDCC4_BCR] = { 0x16000 },
3714 [GCC_TSIF_BCR] = { 0x36000 },
3715 [GCC_UFS_CARD_BCR] = { 0x75000 },
3716 [GCC_UFS_PHY_BCR] = { 0x77000 },
3717 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3718 [GCC_USB30_SEC_BCR] = { 0x10000 },
3719 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3720 [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
3721 [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
3722 [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
3762 .max_register = 0x9c040,
3792 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sm8150_probe()
3793 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sm8150_probe()