Lines Matching +full:0 +full:x33000
38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x76000,
58 .enable_reg = 0x52000,
72 .offset = 0x13000,
75 .enable_reg = 0x52000,
89 { 0x0, 1 },
90 { 0x1, 2 },
91 { 0x3, 4 },
92 { 0x7, 8 },
97 .offset = 0x0,
114 { P_BI_TCXO, 0 },
126 { P_BI_TCXO, 0 },
140 { P_BI_TCXO, 0 },
150 { P_BI_TCXO, 0 },
160 { P_BI_TCXO, 0 },
168 { P_BI_TCXO, 0 },
201 { P_BI_TCXO, 0 },
215 { P_BI_TCXO, 0 },
229 F(19200000, P_BI_TCXO, 1, 0, 0),
234 .cmd_rcgr = 0x48014,
235 .mnd_width = 0,
248 F(19200000, P_BI_TCXO, 1, 0, 0),
253 .cmd_rcgr = 0x4815c,
254 .mnd_width = 0,
267 F(19200000, P_BI_TCXO, 1, 0, 0),
268 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
273 .cmd_rcgr = 0x4815c,
274 .mnd_width = 0,
291 .cmd_rcgr = 0x64004,
305 .cmd_rcgr = 0x65004,
319 .cmd_rcgr = 0x66004,
333 F(9600000, P_BI_TCXO, 2, 0, 0),
334 F(19200000, P_BI_TCXO, 1, 0, 0),
339 .cmd_rcgr = 0x6b028,
353 .cmd_rcgr = 0x8d028,
367 F(19200000, P_BI_TCXO, 1, 0, 0),
368 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
373 .cmd_rcgr = 0x6f014,
374 .mnd_width = 0,
387 F(19200000, P_BI_TCXO, 1, 0, 0),
388 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
389 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
390 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
395 .cmd_rcgr = 0x4b008,
396 .mnd_width = 0,
409 F(9600000, P_BI_TCXO, 2, 0, 0),
410 F(19200000, P_BI_TCXO, 1, 0, 0),
411 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
416 .cmd_rcgr = 0x33010,
417 .mnd_width = 0,
432 F(19200000, P_BI_TCXO, 1, 0, 0),
439 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
443 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
456 .cmd_rcgr = 0x17034,
472 .cmd_rcgr = 0x17164,
488 .cmd_rcgr = 0x17294,
504 .cmd_rcgr = 0x173c4,
520 .cmd_rcgr = 0x174f4,
536 .cmd_rcgr = 0x17624,
552 .cmd_rcgr = 0x17754,
568 .cmd_rcgr = 0x17884,
584 .cmd_rcgr = 0x18018,
600 .cmd_rcgr = 0x18148,
616 .cmd_rcgr = 0x18278,
632 .cmd_rcgr = 0x183a8,
648 .cmd_rcgr = 0x184d8,
664 .cmd_rcgr = 0x18608,
680 .cmd_rcgr = 0x18738,
696 .cmd_rcgr = 0x18868,
709 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
710 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
711 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
712 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
717 .cmd_rcgr = 0x26028,
731 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
732 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
733 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
734 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
739 .cmd_rcgr = 0x26010,
754 F(9600000, P_BI_TCXO, 2, 0, 0),
755 F(19200000, P_BI_TCXO, 1, 0, 0),
756 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
757 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
758 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
759 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
764 .cmd_rcgr = 0x1400c,
779 F(9600000, P_BI_TCXO, 2, 0, 0),
780 F(19200000, P_BI_TCXO, 1, 0, 0),
782 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
783 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
788 .cmd_rcgr = 0x1600c,
803 F(9600000, P_BI_TCXO, 2, 0, 0),
804 F(19200000, P_BI_TCXO, 1, 0, 0),
805 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
806 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
807 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
808 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
813 .cmd_rcgr = 0x1600c,
832 .cmd_rcgr = 0x36010,
846 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
847 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
848 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
849 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
850 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
855 .cmd_rcgr = 0x7501c,
869 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
870 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
871 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
872 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
877 .cmd_rcgr = 0x7505c,
878 .mnd_width = 0,
891 .cmd_rcgr = 0x75090,
892 .mnd_width = 0,
905 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
906 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
907 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
912 .cmd_rcgr = 0x75074,
913 .mnd_width = 0,
926 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
927 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
928 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
929 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
930 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
935 .cmd_rcgr = 0x7701c,
949 .cmd_rcgr = 0x7705c,
950 .mnd_width = 0,
963 .cmd_rcgr = 0x77090,
964 .mnd_width = 0,
977 .cmd_rcgr = 0x77074,
978 .mnd_width = 0,
991 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
992 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
993 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
994 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
995 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1000 .cmd_rcgr = 0xf018,
1014 F(19200000, P_BI_TCXO, 1, 0, 0),
1015 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1016 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1017 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1022 .cmd_rcgr = 0xf030,
1023 .mnd_width = 0,
1036 .cmd_rcgr = 0x10018,
1050 .cmd_rcgr = 0x10030,
1051 .mnd_width = 0,
1064 .cmd_rcgr = 0xf05c,
1065 .mnd_width = 0,
1078 .cmd_rcgr = 0x1005c,
1079 .mnd_width = 0,
1092 .cmd_rcgr = 0x7a030,
1093 .mnd_width = 0,
1106 F(19200000, P_BI_TCXO, 1, 0, 0),
1107 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1108 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
1113 .cmd_rcgr = 0x7a018,
1114 .mnd_width = 0,
1127 .halt_reg = 0x90014,
1130 .enable_reg = 0x90014,
1131 .enable_mask = BIT(0),
1140 .halt_reg = 0x82028,
1142 .hwcg_reg = 0x82028,
1145 .enable_reg = 0x82028,
1146 .enable_mask = BIT(0),
1160 .halt_reg = 0x82024,
1162 .hwcg_reg = 0x82024,
1165 .enable_reg = 0x82024,
1166 .enable_mask = BIT(0),
1180 .halt_reg = 0x8201c,
1183 .enable_reg = 0x8201c,
1184 .enable_mask = BIT(0),
1198 .halt_reg = 0x82020,
1201 .enable_reg = 0x82020,
1202 .enable_mask = BIT(0),
1216 .halt_reg = 0x7a050,
1219 .enable_reg = 0x7a050,
1220 .enable_mask = BIT(0),
1234 .halt_reg = 0x38004,
1236 .hwcg_reg = 0x38004,
1239 .enable_reg = 0x52004,
1249 .halt_reg = 0xb008,
1251 .hwcg_reg = 0xb008,
1254 .enable_reg = 0xb008,
1255 .enable_mask = BIT(0),
1265 .halt_reg = 0xb020,
1268 .enable_reg = 0xb020,
1269 .enable_mask = BIT(0),
1278 .halt_reg = 0xb02c,
1281 .enable_reg = 0xb02c,
1282 .enable_mask = BIT(0),
1292 .halt_reg = 0x4100c,
1294 .hwcg_reg = 0x4100c,
1297 .enable_reg = 0x52004,
1307 .halt_reg = 0x41008,
1310 .enable_reg = 0x52004,
1320 .halt_reg = 0x41004,
1323 .enable_reg = 0x52004,
1333 .halt_reg = 0x502c,
1336 .enable_reg = 0x502c,
1337 .enable_mask = BIT(0),
1351 .halt_reg = 0x5030,
1354 .enable_reg = 0x5030,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x48000,
1372 .enable_reg = 0x52004,
1387 .halt_reg = 0x48008,
1390 .enable_reg = 0x48008,
1391 .enable_mask = BIT(0),
1409 .halt_reg = 0x48008,
1412 .enable_reg = 0x48008,
1413 .enable_mask = BIT(0),
1427 .halt_reg = 0x44038,
1430 .enable_reg = 0x44038,
1431 .enable_mask = BIT(0),
1440 .halt_reg = 0xb00c,
1442 .hwcg_reg = 0xb00c,
1445 .enable_reg = 0xb00c,
1446 .enable_mask = BIT(0),
1456 .halt_reg = 0xb024,
1459 .enable_reg = 0xb024,
1460 .enable_mask = BIT(0),
1471 .enable_reg = 0x52004,
1487 .enable_reg = 0x52004,
1501 .halt_reg = 0xb030,
1504 .enable_reg = 0xb030,
1505 .enable_mask = BIT(0),
1515 .halt_reg = 0x64000,
1518 .enable_reg = 0x64000,
1519 .enable_mask = BIT(0),
1533 .halt_reg = 0x65000,
1536 .enable_reg = 0x65000,
1537 .enable_mask = BIT(0),
1551 .halt_reg = 0x66000,
1554 .enable_reg = 0x66000,
1555 .enable_mask = BIT(0),
1569 .halt_reg = 0x71004,
1571 .hwcg_reg = 0x71004,
1574 .enable_reg = 0x71004,
1575 .enable_mask = BIT(0),
1587 .enable_reg = 0x52004,
1603 .enable_reg = 0x52004,
1617 .halt_reg = 0x8c010,
1620 .enable_reg = 0x8c010,
1621 .enable_mask = BIT(0),
1630 .halt_reg = 0x7100c,
1633 .enable_reg = 0x7100c,
1634 .enable_mask = BIT(0),
1643 .halt_reg = 0x71018,
1646 .enable_reg = 0x71018,
1647 .enable_mask = BIT(0),
1656 .halt_reg = 0x7a04c,
1659 .enable_reg = 0x7a04c,
1660 .enable_mask = BIT(0),
1674 .halt_reg = 0x8a008,
1677 .enable_reg = 0x8a008,
1678 .enable_mask = BIT(0),
1687 .halt_reg = 0x8a000,
1689 .hwcg_reg = 0x8a000,
1692 .enable_reg = 0x8a000,
1693 .enable_mask = BIT(0),
1704 .enable_reg = 0x52004,
1714 .halt_reg = 0x8a004,
1716 .hwcg_reg = 0x8a004,
1719 .enable_reg = 0x8a004,
1720 .enable_mask = BIT(0),
1729 .halt_reg = 0x8a154,
1732 .enable_reg = 0x8a154,
1733 .enable_mask = BIT(0),
1742 .halt_reg = 0x8a150,
1745 .enable_reg = 0x8a150,
1746 .enable_mask = BIT(0),
1755 .halt_reg = 0x7a048,
1758 .enable_reg = 0x7a048,
1759 .enable_mask = BIT(0),
1773 .halt_reg = 0x6b01c,
1776 .enable_reg = 0x5200c,
1791 .halt_reg = 0x6b018,
1793 .hwcg_reg = 0x6b018,
1796 .enable_reg = 0x5200c,
1806 .halt_reg = 0x8c00c,
1809 .enable_reg = 0x8c00c,
1810 .enable_mask = BIT(0),
1819 .halt_reg = 0x6b014,
1822 .enable_reg = 0x5200c,
1834 .enable_reg = 0x5200c,
1849 .halt_reg = 0x6b010,
1851 .hwcg_reg = 0x6b010,
1854 .enable_reg = 0x5200c,
1855 .enable_mask = BIT(0),
1864 .halt_reg = 0x6b00c,
1867 .enable_reg = 0x5200c,
1877 .halt_reg = 0x8d01c,
1880 .enable_reg = 0x52004,
1895 .halt_reg = 0x8d018,
1897 .hwcg_reg = 0x8d018,
1900 .enable_reg = 0x52004,
1910 .halt_reg = 0x8c02c,
1913 .enable_reg = 0x8c02c,
1914 .enable_mask = BIT(0),
1923 .halt_reg = 0x8d014,
1926 .enable_reg = 0x52004,
1938 .enable_reg = 0x52004,
1952 .halt_reg = 0x8d010,
1954 .hwcg_reg = 0x8d010,
1957 .enable_reg = 0x52004,
1967 .halt_reg = 0x8d00c,
1970 .enable_reg = 0x52004,
1980 .halt_reg = 0x6f004,
1983 .enable_reg = 0x6f004,
1984 .enable_mask = BIT(0),
1998 .halt_reg = 0x6f02c,
2001 .enable_reg = 0x6f02c,
2002 .enable_mask = BIT(0),
2016 .halt_reg = 0x3300c,
2019 .enable_reg = 0x3300c,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x33004,
2036 .hwcg_reg = 0x33004,
2039 .enable_reg = 0x33004,
2040 .enable_mask = BIT(0),
2049 .halt_reg = 0x33008,
2052 .enable_reg = 0x33008,
2053 .enable_mask = BIT(0),
2062 .halt_reg = 0x34004,
2064 .hwcg_reg = 0x34004,
2067 .enable_reg = 0x52004,
2077 .halt_reg = 0xb014,
2079 .hwcg_reg = 0xb014,
2082 .enable_reg = 0xb014,
2083 .enable_mask = BIT(0),
2092 .halt_reg = 0xb018,
2094 .hwcg_reg = 0xb018,
2097 .enable_reg = 0xb018,
2098 .enable_mask = BIT(0),
2107 .halt_reg = 0xb010,
2109 .hwcg_reg = 0xb010,
2112 .enable_reg = 0xb010,
2113 .enable_mask = BIT(0),
2122 .halt_reg = 0x4b000,
2125 .enable_reg = 0x4b000,
2126 .enable_mask = BIT(0),
2135 .halt_reg = 0x4b004,
2138 .enable_reg = 0x4b004,
2139 .enable_mask = BIT(0),
2153 .halt_reg = 0x17030,
2156 .enable_reg = 0x5200c,
2171 .halt_reg = 0x17160,
2174 .enable_reg = 0x5200c,
2189 .halt_reg = 0x17290,
2192 .enable_reg = 0x5200c,
2207 .halt_reg = 0x173c0,
2210 .enable_reg = 0x5200c,
2225 .halt_reg = 0x174f0,
2228 .enable_reg = 0x5200c,
2243 .halt_reg = 0x17620,
2246 .enable_reg = 0x5200c,
2261 .halt_reg = 0x17750,
2264 .enable_reg = 0x5200c,
2279 .halt_reg = 0x17880,
2282 .enable_reg = 0x5200c,
2297 .halt_reg = 0x18014,
2300 .enable_reg = 0x5200c,
2315 .halt_reg = 0x18144,
2318 .enable_reg = 0x5200c,
2333 .halt_reg = 0x18274,
2336 .enable_reg = 0x5200c,
2351 .halt_reg = 0x183a4,
2354 .enable_reg = 0x5200c,
2369 .halt_reg = 0x184d4,
2372 .enable_reg = 0x5200c,
2387 .halt_reg = 0x18604,
2390 .enable_reg = 0x5200c,
2405 .halt_reg = 0x18734,
2408 .enable_reg = 0x5200c,
2423 .halt_reg = 0x18864,
2426 .enable_reg = 0x5200c,
2441 .halt_reg = 0x17004,
2444 .enable_reg = 0x5200c,
2454 .halt_reg = 0x17008,
2456 .hwcg_reg = 0x17008,
2459 .enable_reg = 0x5200c,
2469 .halt_reg = 0x1800c,
2472 .enable_reg = 0x5200c,
2482 .halt_reg = 0x18010,
2484 .hwcg_reg = 0x18010,
2487 .enable_reg = 0x5200c,
2497 .halt_reg = 0x26008,
2500 .enable_reg = 0x26008,
2501 .enable_mask = BIT(0),
2510 .halt_reg = 0x26004,
2513 .enable_reg = 0x26004,
2514 .enable_mask = BIT(0),
2528 .halt_reg = 0x2600c,
2531 .enable_reg = 0x2600c,
2532 .enable_mask = BIT(0),
2546 .halt_reg = 0x14008,
2549 .enable_reg = 0x14008,
2550 .enable_mask = BIT(0),
2559 .halt_reg = 0x14004,
2562 .enable_reg = 0x14004,
2563 .enable_mask = BIT(0),
2577 .halt_reg = 0x16008,
2580 .enable_reg = 0x16008,
2581 .enable_mask = BIT(0),
2590 .halt_reg = 0x16004,
2593 .enable_reg = 0x16004,
2594 .enable_mask = BIT(0),
2612 .halt_reg = 0x16004,
2615 .enable_reg = 0x16004,
2616 .enable_mask = BIT(0),
2630 .halt_reg = 0x414c,
2633 .enable_reg = 0x52004,
2634 .enable_mask = BIT(0),
2648 .halt_reg = 0x36004,
2651 .enable_reg = 0x36004,
2652 .enable_mask = BIT(0),
2661 .halt_reg = 0x3600c,
2664 .enable_reg = 0x3600c,
2665 .enable_mask = BIT(0),
2674 .halt_reg = 0x36008,
2677 .enable_reg = 0x36008,
2678 .enable_mask = BIT(0),
2692 .halt_reg = 0x75010,
2694 .hwcg_reg = 0x75010,
2697 .enable_reg = 0x75010,
2698 .enable_mask = BIT(0),
2707 .halt_reg = 0x7500c,
2709 .hwcg_reg = 0x7500c,
2712 .enable_reg = 0x7500c,
2713 .enable_mask = BIT(0),
2727 .halt_reg = 0x8c004,
2730 .enable_reg = 0x8c004,
2731 .enable_mask = BIT(0),
2740 .halt_reg = 0x75058,
2742 .hwcg_reg = 0x75058,
2745 .enable_reg = 0x75058,
2746 .enable_mask = BIT(0),
2760 .halt_reg = 0x7508c,
2762 .hwcg_reg = 0x7508c,
2765 .enable_reg = 0x7508c,
2766 .enable_mask = BIT(0),
2782 .enable_reg = 0x75018,
2783 .enable_mask = BIT(0),
2794 .enable_reg = 0x750a8,
2795 .enable_mask = BIT(0),
2806 .enable_reg = 0x75014,
2807 .enable_mask = BIT(0),
2816 .halt_reg = 0x75054,
2818 .hwcg_reg = 0x75054,
2821 .enable_reg = 0x75054,
2822 .enable_mask = BIT(0),
2836 .halt_reg = 0x8c000,
2839 .enable_reg = 0x8c000,
2840 .enable_mask = BIT(0),
2849 .halt_reg = 0x77010,
2851 .hwcg_reg = 0x77010,
2854 .enable_reg = 0x77010,
2855 .enable_mask = BIT(0),
2864 .halt_reg = 0x7700c,
2866 .hwcg_reg = 0x7700c,
2869 .enable_reg = 0x7700c,
2870 .enable_mask = BIT(0),
2884 .halt_reg = 0x77058,
2886 .hwcg_reg = 0x77058,
2889 .enable_reg = 0x77058,
2890 .enable_mask = BIT(0),
2904 .halt_reg = 0x7708c,
2906 .hwcg_reg = 0x7708c,
2909 .enable_reg = 0x7708c,
2910 .enable_mask = BIT(0),
2926 .enable_reg = 0x77018,
2927 .enable_mask = BIT(0),
2938 .enable_reg = 0x770a8,
2939 .enable_mask = BIT(0),
2950 .enable_reg = 0x77014,
2951 .enable_mask = BIT(0),
2960 .halt_reg = 0x77054,
2962 .hwcg_reg = 0x77054,
2965 .enable_reg = 0x77054,
2966 .enable_mask = BIT(0),
2980 .halt_reg = 0xf00c,
2983 .enable_reg = 0xf00c,
2984 .enable_mask = BIT(0),
2998 .halt_reg = 0xf014,
3001 .enable_reg = 0xf014,
3002 .enable_mask = BIT(0),
3016 .halt_reg = 0xf010,
3019 .enable_reg = 0xf010,
3020 .enable_mask = BIT(0),
3029 .halt_reg = 0x1000c,
3032 .enable_reg = 0x1000c,
3033 .enable_mask = BIT(0),
3047 .halt_reg = 0x10014,
3050 .enable_reg = 0x10014,
3051 .enable_mask = BIT(0),
3065 .halt_reg = 0x10010,
3068 .enable_reg = 0x10010,
3069 .enable_mask = BIT(0),
3078 .halt_reg = 0x8c008,
3081 .enable_reg = 0x8c008,
3082 .enable_mask = BIT(0),
3091 .halt_reg = 0xf04c,
3094 .enable_reg = 0xf04c,
3095 .enable_mask = BIT(0),
3109 .halt_reg = 0xf050,
3112 .enable_reg = 0xf050,
3113 .enable_mask = BIT(0),
3129 .enable_reg = 0xf054,
3130 .enable_mask = BIT(0),
3139 .halt_reg = 0x8c028,
3142 .enable_reg = 0x8c028,
3143 .enable_mask = BIT(0),
3152 .halt_reg = 0x1004c,
3155 .enable_reg = 0x1004c,
3156 .enable_mask = BIT(0),
3170 .halt_reg = 0x10050,
3173 .enable_reg = 0x10050,
3174 .enable_mask = BIT(0),
3190 .enable_reg = 0x10054,
3191 .enable_mask = BIT(0),
3200 .halt_reg = 0x6a004,
3202 .hwcg_reg = 0x6a004,
3205 .enable_reg = 0x6a004,
3206 .enable_mask = BIT(0),
3215 .halt_reg = 0x7a00c,
3218 .enable_reg = 0x7a00c,
3219 .enable_mask = BIT(0),
3233 .halt_reg = 0x7a004,
3236 .enable_reg = 0x7a004,
3237 .enable_mask = BIT(0),
3251 .halt_reg = 0x7a008,
3254 .enable_reg = 0x7a008,
3255 .enable_mask = BIT(0),
3269 .halt_reg = 0xb004,
3271 .hwcg_reg = 0xb004,
3274 .enable_reg = 0xb004,
3275 .enable_mask = BIT(0),
3285 .halt_reg = 0xb01c,
3288 .enable_reg = 0xb01c,
3289 .enable_mask = BIT(0),
3298 .halt_reg = 0xb028,
3301 .enable_reg = 0xb028,
3302 .enable_mask = BIT(0),
3312 .halt_reg = 0x7a014,
3314 .hwcg_reg = 0x7a014,
3317 .enable_reg = 0x7a014,
3318 .enable_mask = BIT(0),
3327 .halt_reg = 0x7a010,
3330 .enable_reg = 0x7a010,
3331 .enable_mask = BIT(0),
3345 .halt_reg = 0x48190,
3348 .enable_reg = 0x48190,
3349 .enable_mask = BIT(0),
3359 .halt_reg = 0x48004,
3361 .hwcg_reg = 0x48004,
3364 .enable_reg = 0x52004,
3377 .halt_reg = 0x47000,
3380 .enable_reg = 0x47000,
3381 .enable_mask = BIT(0),
3391 .halt_reg = 0x47008,
3394 .enable_reg = 0x47008,
3395 .enable_mask = BIT(0),
3406 .gdscr = 0x6b004,
3415 .gdscr = 0x8d004,
3424 .gdscr = 0x75004,
3433 .gdscr = 0x77004,
3442 .gdscr = 0xf004,
3451 .gdscr = 0x10004,
3460 .gdscr = 0x7d030,
3469 .gdscr = 0x7d03c,
3478 .gdscr = 0x7d034,
3487 .gdscr = 0x7d038,
3496 .gdscr = 0x7d040,
3505 .gdscr = 0x7d048,
3514 .gdscr = 0x7d044,
3868 [GCC_MMSS_BCR] = { 0xb000 },
3869 [GCC_PCIE_0_BCR] = { 0x6b000 },
3870 [GCC_PCIE_1_BCR] = { 0x8d000 },
3871 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3872 [GCC_PDM_BCR] = { 0x33000 },
3873 [GCC_PRNG_BCR] = { 0x34000 },
3874 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3875 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3876 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3877 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3878 [GCC_SDCC2_BCR] = { 0x14000 },
3879 [GCC_SDCC4_BCR] = { 0x16000 },
3880 [GCC_TSIF_BCR] = { 0x36000 },
3881 [GCC_UFS_CARD_BCR] = { 0x75000 },
3882 [GCC_UFS_PHY_BCR] = { 0x77000 },
3883 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3884 [GCC_USB30_SEC_BCR] = { 0x10000 },
3885 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3886 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3887 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3888 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3889 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3890 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3891 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3892 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3893 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3938 .max_register = 0x182090,
4000 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sdm845_probe()
4001 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sdm845_probe()