Lines Matching +full:0 +full:x18140
45 .offset = 0x0,
48 .enable_reg = 0x52010,
49 .enable_mask = BIT(0),
62 { 0x1, 2 },
67 .offset = 0x0,
84 { 0x3, 3 },
89 .offset = 0x0,
106 .offset = 0x1000,
109 .enable_reg = 0x52010,
123 .offset = 0x1e000,
126 .enable_reg = 0x52010,
140 .offset = 0x76000,
143 .enable_reg = 0x52010,
157 .offset = 0x1c000,
160 .enable_reg = 0x52010,
176 .enable_reg = 0x52000,
191 { P_BI_TCXO, 0 },
203 { P_BI_TCXO, 0 },
217 { P_BI_TCXO, 0 },
227 { P_BI_TCXO, 0 },
235 { P_BI_TCXO, 0 },
251 { P_BI_TCXO, 0 },
261 { P_BI_TCXO, 0 },
277 { P_BI_TCXO, 0 },
295 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
305 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
315 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
325 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
335 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
345 { P_BI_TCXO, 0 },
355 .reg = 0x6b054,
370 .reg = 0x8d054,
385 .reg = 0x77058,
386 .shift = 0,
400 .reg = 0x770c8,
401 .shift = 0,
415 .reg = 0x77048,
416 .shift = 0,
430 .reg = 0xf060,
431 .shift = 0,
445 .reg = 0x9e060,
446 .shift = 0,
460 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
461 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
462 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
467 .cmd_rcgr = 0x64004,
481 .cmd_rcgr = 0x65004,
495 .cmd_rcgr = 0x66004,
509 F(9600000, P_BI_TCXO, 2, 0, 0),
510 F(19200000, P_BI_TCXO, 1, 0, 0),
515 .cmd_rcgr = 0x6b058,
529 F(19200000, P_BI_TCXO, 1, 0, 0),
530 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
535 .cmd_rcgr = 0x6b03c,
536 .mnd_width = 0,
549 .cmd_rcgr = 0x8d058,
563 .cmd_rcgr = 0x8d03c,
564 .mnd_width = 0,
578 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
583 .cmd_rcgr = 0x33010,
584 .mnd_width = 0,
598 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
599 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
600 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
601 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
606 .cmd_rcgr = 0x4b00c,
607 .mnd_width = 0,
622 F(19200000, P_BI_TCXO, 1, 0, 0),
627 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
630 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
634 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
646 .cmd_rcgr = 0x17010,
662 .cmd_rcgr = 0x17140,
673 F(19200000, P_BI_TCXO, 1, 0, 0),
679 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
682 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
694 .cmd_rcgr = 0x17270,
710 .cmd_rcgr = 0x173a0,
726 .cmd_rcgr = 0x174d0,
742 .cmd_rcgr = 0x17600,
758 .cmd_rcgr = 0x17730,
774 .cmd_rcgr = 0x17860,
790 .cmd_rcgr = 0x18010,
806 .cmd_rcgr = 0x18140,
822 .cmd_rcgr = 0x18270,
838 .cmd_rcgr = 0x183a0,
854 .cmd_rcgr = 0x184d0,
870 .cmd_rcgr = 0x18600,
886 .cmd_rcgr = 0x18730,
902 .cmd_rcgr = 0x18860,
913 F(19200000, P_BI_TCXO, 1, 0, 0),
915 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
916 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
917 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
918 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
919 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
924 .cmd_rcgr = 0x7500c,
938 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
939 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
940 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
945 .cmd_rcgr = 0x7502c,
946 .mnd_width = 0,
960 F(19200000, P_BI_TCXO, 1, 0, 0),
961 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
962 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
963 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
964 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
969 .cmd_rcgr = 0x1400c,
985 F(19200000, P_BI_TCXO, 1, 0, 0),
986 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
987 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
988 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
993 .cmd_rcgr = 0x1600c,
1007 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1008 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1009 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1010 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1015 .cmd_rcgr = 0x77024,
1029 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1030 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1031 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1036 .cmd_rcgr = 0x7706c,
1037 .mnd_width = 0,
1050 .cmd_rcgr = 0x770a0,
1051 .mnd_width = 0,
1064 .cmd_rcgr = 0x77084,
1065 .mnd_width = 0,
1078 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1079 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1080 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1081 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1086 .cmd_rcgr = 0xf020,
1100 F(19200000, P_BI_TCXO, 1, 0, 0),
1105 .cmd_rcgr = 0xf038,
1106 .mnd_width = 0,
1119 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1120 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1125 .cmd_rcgr = 0x9e020,
1139 .cmd_rcgr = 0x9e038,
1140 .mnd_width = 0,
1153 .cmd_rcgr = 0xf064,
1154 .mnd_width = 0,
1167 .cmd_rcgr = 0x9e064,
1168 .mnd_width = 0,
1181 F(4800000, P_BI_TCXO, 4, 0, 0),
1182 F(19200000, P_BI_TCXO, 1, 0, 0),
1187 .cmd_rcgr = 0x3d02c,
1188 .mnd_width = 0,
1201 .reg = 0xf050,
1202 .shift = 0,
1216 .reg = 0x9e050,
1217 .shift = 0,
1231 .halt_reg = 0x8c004,
1234 .enable_reg = 0x8c004,
1235 .enable_mask = BIT(0),
1244 .halt_reg = 0x8c008,
1247 .enable_reg = 0x8c008,
1248 .enable_mask = BIT(0),
1257 .halt_reg = 0x6b080,
1259 .hwcg_reg = 0x6b080,
1262 .enable_reg = 0x52000,
1272 .halt_reg = 0x8d084,
1274 .hwcg_reg = 0x8d084,
1277 .enable_reg = 0x52000,
1287 .halt_reg = 0x90010,
1289 .hwcg_reg = 0x90010,
1292 .enable_reg = 0x52000,
1302 .halt_reg = 0x8d088,
1304 .hwcg_reg = 0x8d088,
1307 .enable_reg = 0x52008,
1317 .halt_reg = 0x770cc,
1319 .hwcg_reg = 0x770cc,
1322 .enable_reg = 0x770cc,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0xf080,
1339 .hwcg_reg = 0xf080,
1342 .enable_reg = 0xf080,
1343 .enable_mask = BIT(0),
1357 .halt_reg = 0x9e080,
1359 .hwcg_reg = 0x9e080,
1362 .enable_reg = 0x9e080,
1363 .enable_mask = BIT(0),
1377 .halt_reg = 0x26010,
1379 .hwcg_reg = 0x26010,
1382 .enable_reg = 0x26010,
1383 .enable_mask = BIT(0),
1392 .halt_reg = 0x2601c,
1394 .hwcg_reg = 0x2601c,
1397 .enable_reg = 0x2601c,
1398 .enable_mask = BIT(0),
1407 .halt_reg = 0xf07c,
1409 .hwcg_reg = 0xf07c,
1412 .enable_reg = 0xf07c,
1413 .enable_mask = BIT(0),
1427 .halt_reg = 0x9e07c,
1429 .hwcg_reg = 0x9e07c,
1432 .enable_reg = 0x9e07c,
1433 .enable_mask = BIT(0),
1447 .halt_reg = 0x71154,
1449 .hwcg_reg = 0x71154,
1452 .enable_reg = 0x71154,
1453 .enable_mask = BIT(0),
1462 .halt_reg = 0x8d080,
1464 .hwcg_reg = 0x8d080,
1467 .enable_reg = 0x52000,
1479 .enable_reg = 0x52000,
1494 .halt_reg = 0x2700c,
1496 .hwcg_reg = 0x2700c,
1499 .enable_reg = 0x2700c,
1500 .enable_mask = BIT(0),
1509 .halt_reg = 0x27014,
1511 .hwcg_reg = 0x27014,
1514 .enable_reg = 0x27014,
1515 .enable_mask = BIT(0),
1524 .halt_reg = 0x64000,
1527 .enable_reg = 0x64000,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0x65000,
1545 .enable_reg = 0x65000,
1546 .enable_mask = BIT(0),
1560 .halt_reg = 0x66000,
1563 .enable_reg = 0x66000,
1564 .enable_mask = BIT(0),
1580 .enable_reg = 0x52000,
1597 .enable_reg = 0x52000,
1612 .halt_reg = 0x8c014,
1615 .enable_reg = 0x8c014,
1616 .enable_mask = BIT(0),
1625 .halt_reg = 0x7100c,
1627 .hwcg_reg = 0x7100c,
1630 .enable_reg = 0x7100c,
1631 .enable_mask = BIT(0),
1640 .halt_reg = 0x71018,
1643 .enable_reg = 0x71018,
1644 .enable_mask = BIT(0),
1653 .halt_reg = 0x6b038,
1656 .enable_reg = 0x52000,
1671 .halt_reg = 0x8d038,
1674 .enable_reg = 0x52000,
1689 .halt_reg = 0x6b028,
1692 .enable_reg = 0x52008,
1707 .halt_reg = 0x6b024,
1709 .hwcg_reg = 0x6b024,
1712 .enable_reg = 0x52008,
1722 .halt_reg = 0x6b01c,
1725 .enable_reg = 0x52008,
1735 .halt_reg = 0x6b030,
1738 .enable_reg = 0x52008,
1753 .halt_reg = 0x6b014,
1756 .enable_reg = 0x52008,
1757 .enable_mask = BIT(0),
1766 .halt_reg = 0x6b010,
1769 .enable_reg = 0x52008,
1779 .halt_reg = 0x8d028,
1782 .enable_reg = 0x52000,
1797 .halt_reg = 0x8d024,
1799 .hwcg_reg = 0x8d024,
1802 .enable_reg = 0x52000,
1812 .halt_reg = 0x8d01c,
1815 .enable_reg = 0x52000,
1825 .halt_reg = 0x8d030,
1828 .enable_reg = 0x52000,
1843 .halt_reg = 0x8d014,
1846 .enable_reg = 0x52000,
1856 .halt_reg = 0x8d010,
1859 .enable_reg = 0x52000,
1869 .halt_reg = 0x90018,
1871 .hwcg_reg = 0x90018,
1874 .enable_reg = 0x52000,
1884 .halt_reg = 0x3300c,
1887 .enable_reg = 0x3300c,
1888 .enable_mask = BIT(0),
1902 .halt_reg = 0x33004,
1904 .hwcg_reg = 0x33004,
1907 .enable_reg = 0x33004,
1908 .enable_mask = BIT(0),
1917 .halt_reg = 0x33008,
1920 .enable_reg = 0x33008,
1921 .enable_mask = BIT(0),
1930 .halt_reg = 0x26008,
1932 .hwcg_reg = 0x26008,
1935 .enable_reg = 0x26008,
1936 .enable_mask = BIT(0),
1945 .halt_reg = 0x2600c,
1947 .hwcg_reg = 0x2600c,
1950 .enable_reg = 0x2600c,
1951 .enable_mask = BIT(0),
1960 .halt_reg = 0x27008,
1963 .enable_reg = 0x27008,
1964 .enable_mask = BIT(0),
1973 .halt_reg = 0x28008,
1975 .hwcg_reg = 0x28008,
1978 .enable_reg = 0x28008,
1979 .enable_mask = BIT(0),
1988 .halt_reg = 0x4b004,
1990 .hwcg_reg = 0x4b004,
1993 .enable_reg = 0x4b004,
1994 .enable_mask = BIT(0),
2003 .halt_reg = 0x4b008,
2006 .enable_reg = 0x4b008,
2007 .enable_mask = BIT(0),
2021 .halt_reg = 0x23008,
2024 .enable_reg = 0x52008,
2034 .halt_reg = 0x23000,
2037 .enable_reg = 0x52008,
2047 .halt_reg = 0x1700c,
2050 .enable_reg = 0x52008,
2065 .halt_reg = 0x1713c,
2068 .enable_reg = 0x52008,
2083 .halt_reg = 0x1726c,
2086 .enable_reg = 0x52008,
2101 .halt_reg = 0x1739c,
2104 .enable_reg = 0x52008,
2119 .halt_reg = 0x174cc,
2122 .enable_reg = 0x52008,
2137 .halt_reg = 0x175fc,
2140 .enable_reg = 0x52008,
2155 .halt_reg = 0x1772c,
2158 .enable_reg = 0x52008,
2173 .halt_reg = 0x1785c,
2176 .enable_reg = 0x52008,
2191 .halt_reg = 0x23140,
2194 .enable_reg = 0x52008,
2204 .halt_reg = 0x23138,
2207 .enable_reg = 0x52008,
2217 .halt_reg = 0x1800c,
2220 .enable_reg = 0x52008,
2235 .halt_reg = 0x1813c,
2238 .enable_reg = 0x52008,
2253 .halt_reg = 0x1826c,
2256 .enable_reg = 0x52008,
2271 .halt_reg = 0x1839c,
2274 .enable_reg = 0x52008,
2289 .halt_reg = 0x184cc,
2292 .enable_reg = 0x52008,
2307 .halt_reg = 0x185fc,
2310 .enable_reg = 0x52008,
2325 .halt_reg = 0x1872c,
2328 .enable_reg = 0x52000,
2343 .halt_reg = 0x1885c,
2346 .enable_reg = 0x52000,
2361 .halt_reg = 0x17004,
2363 .hwcg_reg = 0x17004,
2366 .enable_reg = 0x52008,
2376 .halt_reg = 0x17008,
2378 .hwcg_reg = 0x17008,
2381 .enable_reg = 0x52008,
2391 .halt_reg = 0x18004,
2393 .hwcg_reg = 0x18004,
2396 .enable_reg = 0x52008,
2406 .halt_reg = 0x18008,
2408 .hwcg_reg = 0x18008,
2411 .enable_reg = 0x52008,
2421 .halt_reg = 0x75004,
2424 .enable_reg = 0x75004,
2425 .enable_mask = BIT(0),
2434 .halt_reg = 0x75008,
2437 .enable_reg = 0x75008,
2438 .enable_mask = BIT(0),
2452 .halt_reg = 0x75024,
2454 .hwcg_reg = 0x75024,
2457 .enable_reg = 0x75024,
2458 .enable_mask = BIT(0),
2472 .halt_reg = 0x14008,
2475 .enable_reg = 0x14008,
2476 .enable_mask = BIT(0),
2485 .halt_reg = 0x14004,
2488 .enable_reg = 0x14004,
2489 .enable_mask = BIT(0),
2503 .halt_reg = 0x16008,
2506 .enable_reg = 0x16008,
2507 .enable_mask = BIT(0),
2516 .halt_reg = 0x16004,
2519 .enable_reg = 0x16004,
2520 .enable_mask = BIT(0),
2534 .halt_reg = 0x9001c,
2537 .enable_reg = 0x9001c,
2538 .enable_mask = BIT(0),
2547 .halt_reg = 0x26024,
2549 .hwcg_reg = 0x26024,
2552 .enable_reg = 0x26024,
2553 .enable_mask = BIT(0),
2562 .halt_reg = 0x26018,
2564 .hwcg_reg = 0x26018,
2567 .enable_reg = 0x26018,
2568 .enable_mask = BIT(0),
2577 .halt_reg = 0x8c000,
2580 .enable_reg = 0x8c000,
2581 .enable_mask = BIT(0),
2590 .halt_reg = 0x77018,
2592 .hwcg_reg = 0x77018,
2595 .enable_reg = 0x77018,
2596 .enable_mask = BIT(0),
2605 .halt_reg = 0x77010,
2607 .hwcg_reg = 0x77010,
2610 .enable_reg = 0x77010,
2611 .enable_mask = BIT(0),
2625 .halt_reg = 0x77064,
2627 .hwcg_reg = 0x77064,
2630 .enable_reg = 0x77064,
2631 .enable_mask = BIT(0),
2645 .halt_reg = 0x7709c,
2647 .hwcg_reg = 0x7709c,
2650 .enable_reg = 0x7709c,
2651 .enable_mask = BIT(0),
2665 .halt_reg = 0x77020,
2668 .enable_reg = 0x77020,
2669 .enable_mask = BIT(0),
2683 .halt_reg = 0x770b8,
2686 .enable_reg = 0x770b8,
2687 .enable_mask = BIT(0),
2701 .halt_reg = 0x7701c,
2704 .enable_reg = 0x7701c,
2705 .enable_mask = BIT(0),
2719 .halt_reg = 0x7705c,
2721 .hwcg_reg = 0x7705c,
2724 .enable_reg = 0x7705c,
2725 .enable_mask = BIT(0),
2739 .halt_reg = 0xf010,
2742 .enable_reg = 0xf010,
2743 .enable_mask = BIT(0),
2757 .halt_reg = 0xf01c,
2760 .enable_reg = 0xf01c,
2761 .enable_mask = BIT(0),
2775 .halt_reg = 0xf018,
2778 .enable_reg = 0xf018,
2779 .enable_mask = BIT(0),
2788 .halt_reg = 0x9e010,
2791 .enable_reg = 0x9e010,
2792 .enable_mask = BIT(0),
2806 .halt_reg = 0x9e01c,
2809 .enable_reg = 0x9e01c,
2810 .enable_mask = BIT(0),
2824 .halt_reg = 0x9e018,
2827 .enable_reg = 0x9e018,
2828 .enable_mask = BIT(0),
2837 .halt_reg = 0xf054,
2840 .enable_reg = 0xf054,
2841 .enable_mask = BIT(0),
2855 .halt_reg = 0xf058,
2858 .enable_reg = 0xf058,
2859 .enable_mask = BIT(0),
2873 .halt_reg = 0xf05c,
2875 .hwcg_reg = 0xf05c,
2878 .enable_reg = 0xf05c,
2879 .enable_mask = BIT(0),
2893 .halt_reg = 0x47020,
2896 .enable_reg = 0x47020,
2897 .enable_mask = BIT(0),
2905 .halt_reg = 0x8a000,
2908 .enable_reg = 0x8a000,
2909 .enable_mask = BIT(0),
2918 .halt_reg = 0x8a004,
2921 .enable_reg = 0x8a004,
2922 .enable_mask = BIT(0),
2931 .halt_reg = 0x8a154,
2934 .enable_reg = 0x8a154,
2935 .enable_mask = BIT(0),
2944 .halt_reg = 0x8a158,
2947 .enable_reg = 0x8a158,
2948 .enable_mask = BIT(0),
2957 .reg = 0x8a2a4,
2958 .shift = 0,
2972 .halt_reg = 0x9e054,
2975 .enable_reg = 0x9e054,
2976 .enable_mask = BIT(0),
2990 .halt_reg = 0x9e058,
2993 .enable_reg = 0x9e058,
2994 .enable_mask = BIT(0),
3008 .halt_reg = 0x9e05c,
3010 .hwcg_reg = 0x9e05c,
3013 .enable_reg = 0x9e05c,
3014 .enable_mask = BIT(0),
3028 .halt_reg = 0x2800c,
3030 .hwcg_reg = 0x2800c,
3033 .enable_reg = 0x2800c,
3034 .enable_mask = BIT(0),
3043 .halt_reg = 0x28010,
3045 .hwcg_reg = 0x28010,
3048 .enable_reg = 0x28010,
3049 .enable_mask = BIT(0),
3058 .halt_reg = 0x9d154,
3061 .enable_reg = 0x9d154,
3062 .enable_mask = BIT(0),
3071 .halt_reg = 0x9d158,
3074 .enable_reg = 0x9d158,
3075 .enable_mask = BIT(0),
3084 .halt_reg = 0x9d16c,
3087 .enable_reg = 0x9d16c,
3088 .enable_mask = BIT(0),
3097 .gdscr = 0x6b004,
3098 .en_rest_wait_val = 0x2,
3099 .en_few_wait_val = 0x2,
3100 .clk_dis_wait_val = 0xf,
3109 .gdscr = 0x8d004,
3118 .gdscr = 0x77004,
3119 .en_rest_wait_val = 0x2,
3120 .en_few_wait_val = 0x2,
3121 .clk_dis_wait_val = 0xf,
3130 .gdscr = 0xf004,
3131 .en_rest_wait_val = 0x2,
3132 .en_few_wait_val = 0x2,
3133 .clk_dis_wait_val = 0xf,
3142 .gdscr = 0x9e004,
3151 .gdscr = 0x7d050,
3160 .gdscr = 0x7d058,
3169 .gdscr = 0x7d054,
3178 .gdscr = 0x7d05c,
3187 .gdscr = 0x7d060,
3396 [GCC_PCIE_0_BCR] = { 0x6b000 },
3397 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3398 [GCC_PCIE_1_BCR] = { 0x8d000 },
3399 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3400 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3401 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3402 [GCC_SDCC1_BCR] = { 0x75000 },
3403 [GCC_SDCC2_BCR] = { 0x14000 },
3404 [GCC_SDCC4_BCR] = { 0x16000 },
3405 [GCC_UFS_PHY_BCR] = { 0x77000 },
3406 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3407 [GCC_USB30_SEC_BCR] = { 0x9e000 },
3408 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3409 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3410 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3411 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3437 .max_register = 0x9f128,
3467 qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */ in gcc_sc7280_probe()
3468 qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */ in gcc_sc7280_probe()
3469 qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */ in gcc_sc7280_probe()
3470 qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */ in gcc_sc7280_probe()
3471 qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */ in gcc_sc7280_probe()
3472 qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */ in gcc_sc7280_probe()
3473 qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ in gcc_sc7280_probe()
3474 regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); in gcc_sc7280_probe()