Lines Matching +full:0 +full:x1f004
60 .offset = 0x0,
63 .enable_reg = 0x4b028,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
99 .offset = 0x1000,
102 .enable_reg = 0x4b028,
116 .offset = 0x4000,
119 .enable_reg = 0x4b028,
133 .offset = 0x7000,
136 .enable_reg = 0x4b028,
150 .offset = 0x9000,
153 .enable_reg = 0x4b028,
167 { P_BI_TCXO, 0 },
179 { P_BI_TCXO, 0 },
193 { P_BI_TCXO, 0 },
203 { P_BI_TCXO, 0 },
219 { P_BI_TCXO, 0 },
233 { P_BI_TCXO, 0 },
241 { P_BI_TCXO, 0 },
255 { P_BI_TCXO, 0 },
289 { P_BI_TCXO, 0 },
305 { P_BI_TCXO, 0 },
315 { P_BI_TCXO, 0 },
329 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
339 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
349 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
359 { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 },
369 .reg = 0xa9074,
370 .shift = 0,
384 .reg = 0xa906c,
398 .reg = 0x77074,
399 .shift = 0,
413 .reg = 0x7706c,
427 .reg = 0x83060,
428 .shift = 0,
442 .reg = 0x830d0,
443 .shift = 0,
457 .reg = 0x83050,
458 .shift = 0,
472 .reg = 0x1b068,
473 .shift = 0,
487 F(19200000, P_BI_TCXO, 1, 0, 0),
492 .cmd_rcgr = 0xb6028,
493 .mnd_width = 0,
507 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
508 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
513 .cmd_rcgr = 0xb6060,
529 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
530 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
531 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
536 .cmd_rcgr = 0xb6048,
551 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
552 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
557 .cmd_rcgr = 0x70004,
572 .cmd_rcgr = 0x71004,
587 .cmd_rcgr = 0x62004,
602 .cmd_rcgr = 0x1e004,
617 .cmd_rcgr = 0x1f004,
632 .cmd_rcgr = 0xa9078,
647 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
652 .cmd_rcgr = 0xa9054,
653 .mnd_width = 0,
667 .cmd_rcgr = 0x77078,
682 .cmd_rcgr = 0x77054,
683 .mnd_width = 0,
697 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
702 .cmd_rcgr = 0x3f010,
703 .mnd_width = 0,
719 F(19200000, P_BI_TCXO, 1, 0, 0),
726 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
739 .cmd_rcgr = 0x23154,
756 .cmd_rcgr = 0x23288,
767 F(19200000, P_BI_TCXO, 1, 0, 0),
774 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
787 .cmd_rcgr = 0x233bc,
804 .cmd_rcgr = 0x234f0,
821 .cmd_rcgr = 0x23624,
838 .cmd_rcgr = 0x23758,
855 .cmd_rcgr = 0x2388c,
872 .cmd_rcgr = 0x239c0,
889 .cmd_rcgr = 0x24154,
906 .cmd_rcgr = 0x24288,
923 .cmd_rcgr = 0x243bc,
940 .cmd_rcgr = 0x244f0,
957 .cmd_rcgr = 0x24624,
974 .cmd_rcgr = 0x24758,
991 .cmd_rcgr = 0x2488c,
1008 .cmd_rcgr = 0x249c0,
1019 F(19200000, P_BI_TCXO, 1, 0, 0),
1024 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1027 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1028 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1041 .cmd_rcgr = 0xc4158,
1052 F(19200000, P_BI_TCXO, 1, 0, 0),
1054 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1055 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1056 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1057 F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1058 F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0),
1063 .cmd_rcgr = 0x20014,
1078 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1079 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1084 .cmd_rcgr = 0x2002c,
1085 .mnd_width = 0,
1099 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1100 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1101 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1102 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1107 .cmd_rcgr = 0x8302c,
1122 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1123 F(201600000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1124 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1129 .cmd_rcgr = 0x83074,
1130 .mnd_width = 0,
1144 .cmd_rcgr = 0x830a8,
1145 .mnd_width = 0,
1159 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1160 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1161 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1166 .cmd_rcgr = 0x8308c,
1167 .mnd_width = 0,
1181 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1186 .cmd_rcgr = 0x1c028,
1201 .cmd_rcgr = 0x1c040,
1202 .mnd_width = 0,
1216 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1217 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1218 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1223 .cmd_rcgr = 0x1b028,
1238 .cmd_rcgr = 0x1b040,
1239 .mnd_width = 0,
1253 .cmd_rcgr = 0x1b06c,
1254 .mnd_width = 0,
1268 .reg = 0xa9070,
1269 .shift = 0,
1283 .reg = 0x77070,
1284 .shift = 0,
1298 .reg = 0xc4288,
1299 .shift = 0,
1313 .reg = 0x1c058,
1314 .shift = 0,
1328 .reg = 0x1b058,
1329 .shift = 0,
1343 .halt_reg = 0x8e200,
1345 .hwcg_reg = 0x8e200,
1348 .enable_reg = 0x4b000,
1358 .halt_reg = 0x830d4,
1360 .hwcg_reg = 0x830d4,
1363 .enable_reg = 0x830d4,
1364 .enable_mask = BIT(0),
1378 .halt_reg = 0x1c05c,
1380 .hwcg_reg = 0x1c05c,
1383 .enable_reg = 0x1c05c,
1384 .enable_mask = BIT(0),
1398 .halt_reg = 0x1b084,
1400 .hwcg_reg = 0x1b084,
1403 .enable_reg = 0x1b084,
1404 .enable_mask = BIT(0),
1418 .halt_reg = 0x76004,
1420 .hwcg_reg = 0x76004,
1423 .enable_reg = 0x76004,
1424 .enable_mask = BIT(0),
1433 .halt_reg = 0x76008,
1435 .hwcg_reg = 0x76008,
1438 .enable_reg = 0x76008,
1439 .enable_mask = BIT(0),
1448 .halt_reg = 0x7600c,
1450 .hwcg_reg = 0x7600c,
1453 .enable_reg = 0x7600c,
1454 .enable_mask = BIT(0),
1463 .halt_reg = 0x44004,
1465 .hwcg_reg = 0x44004,
1468 .enable_reg = 0x4b000,
1478 .halt_reg = 0x32010,
1480 .hwcg_reg = 0x32010,
1483 .enable_reg = 0x32010,
1484 .enable_mask = BIT(0),
1493 .halt_reg = 0x32018,
1495 .hwcg_reg = 0x32018,
1498 .enable_reg = 0x32018,
1499 .enable_mask = BIT(0),
1508 .halt_reg = 0x32024,
1511 .enable_reg = 0x32024,
1512 .enable_mask = BIT(0),
1521 .halt_reg = 0x1c060,
1523 .hwcg_reg = 0x1c060,
1526 .enable_reg = 0x1c060,
1527 .enable_mask = BIT(0),
1541 .halt_reg = 0x1b088,
1543 .hwcg_reg = 0x1b088,
1546 .enable_reg = 0x1b088,
1547 .enable_mask = BIT(0),
1561 .halt_reg = 0x7d164,
1563 .hwcg_reg = 0x7d164,
1566 .enable_reg = 0x7d164,
1567 .enable_mask = BIT(0),
1576 .halt_reg = 0x33010,
1578 .hwcg_reg = 0x33010,
1581 .enable_reg = 0x33010,
1582 .enable_mask = BIT(0),
1591 .halt_reg = 0x97448,
1594 .enable_reg = 0x97448,
1595 .enable_mask = BIT(0),
1604 .halt_reg = 0xb6018,
1606 .hwcg_reg = 0xb6018,
1609 .enable_reg = 0xb6018,
1610 .enable_mask = BIT(0),
1619 .halt_reg = 0xb6024,
1622 .enable_reg = 0xb6024,
1623 .enable_mask = BIT(0),
1637 .halt_reg = 0xb6040,
1640 .enable_reg = 0xb6040,
1641 .enable_mask = BIT(0),
1655 .halt_reg = 0xb6044,
1658 .enable_reg = 0xb6044,
1659 .enable_mask = BIT(0),
1673 .halt_reg = 0xb6020,
1675 .hwcg_reg = 0xb6020,
1678 .enable_reg = 0xb6020,
1679 .enable_mask = BIT(0),
1688 .halt_reg = 0x70000,
1691 .enable_reg = 0x70000,
1692 .enable_mask = BIT(0),
1706 .halt_reg = 0x71000,
1709 .enable_reg = 0x71000,
1710 .enable_mask = BIT(0),
1724 .halt_reg = 0x62000,
1727 .enable_reg = 0x62000,
1728 .enable_mask = BIT(0),
1742 .halt_reg = 0x1e000,
1745 .enable_reg = 0x1e000,
1746 .enable_mask = BIT(0),
1760 .halt_reg = 0x1f000,
1763 .enable_reg = 0x1f000,
1764 .enable_mask = BIT(0),
1780 .enable_reg = 0x4b000,
1797 .enable_reg = 0x4b000,
1812 .halt_reg = 0x7d160,
1814 .hwcg_reg = 0x7d160,
1817 .enable_reg = 0x7d160,
1818 .enable_mask = BIT(0),
1827 .halt_reg = 0x7d010,
1829 .hwcg_reg = 0x7d010,
1832 .enable_reg = 0x7d010,
1833 .enable_mask = BIT(0),
1842 .halt_reg = 0x7d01c,
1845 .enable_reg = 0x7d01c,
1846 .enable_mask = BIT(0),
1855 .halt_reg = 0x7d008,
1857 .hwcg_reg = 0x7d008,
1860 .enable_reg = 0x7d008,
1861 .enable_mask = BIT(0),
1870 .halt_reg = 0x7d014,
1872 .hwcg_reg = 0x7d014,
1875 .enable_reg = 0x7d014,
1876 .enable_mask = BIT(0),
1885 .halt_reg = 0xa9038,
1888 .enable_reg = 0x4b010,
1903 .halt_reg = 0xa902c,
1905 .hwcg_reg = 0xa902c,
1908 .enable_reg = 0x4b010,
1918 .halt_reg = 0xa9024,
1921 .enable_reg = 0x4b010,
1931 .halt_reg = 0xa9030,
1934 .enable_reg = 0x4b010,
1949 .halt_reg = 0xa9050,
1952 .enable_reg = 0x4b010,
1967 .halt_reg = 0xa9040,
1970 .enable_reg = 0x4b010,
1985 .halt_reg = 0xa9048,
1988 .enable_reg = 0x4b018,
2003 .halt_reg = 0xa901c,
2006 .enable_reg = 0x4b010,
2016 .halt_reg = 0xa9018,
2019 .enable_reg = 0x4b018,
2029 .halt_reg = 0x77038,
2032 .enable_reg = 0x4b000,
2047 .halt_reg = 0x7702c,
2049 .hwcg_reg = 0x7702c,
2052 .enable_reg = 0x4b008,
2062 .halt_reg = 0x77024,
2065 .enable_reg = 0x4b008,
2075 .halt_reg = 0x77030,
2078 .enable_reg = 0x4b008,
2093 .halt_reg = 0x77050,
2096 .enable_reg = 0x4b000,
2111 .halt_reg = 0x77040,
2114 .enable_reg = 0x4b008,
2129 .halt_reg = 0x77048,
2132 .enable_reg = 0x4b018,
2147 .halt_reg = 0x7701c,
2150 .enable_reg = 0x4b008,
2151 .enable_mask = BIT(0),
2160 .halt_reg = 0x77018,
2163 .enable_reg = 0x4b008,
2173 .halt_reg = 0x9746c,
2176 .enable_reg = 0x9746c,
2177 .enable_mask = BIT(0),
2186 .halt_reg = 0xb2034,
2189 .enable_reg = 0x4b020,
2199 .halt_reg = 0x3f00c,
2202 .enable_reg = 0x3f00c,
2203 .enable_mask = BIT(0),
2217 .halt_reg = 0x3f004,
2219 .hwcg_reg = 0x3f004,
2222 .enable_reg = 0x3f004,
2223 .enable_mask = BIT(0),
2232 .halt_reg = 0x3f008,
2235 .enable_reg = 0x3f008,
2236 .enable_mask = BIT(0),
2245 .halt_reg = 0x32008,
2247 .hwcg_reg = 0x32008,
2250 .enable_reg = 0x32008,
2251 .enable_mask = BIT(0),
2260 .halt_reg = 0x3200c,
2262 .hwcg_reg = 0x3200c,
2265 .enable_reg = 0x3200c,
2266 .enable_mask = BIT(0),
2275 .halt_reg = 0x33008,
2277 .hwcg_reg = 0x33008,
2280 .enable_reg = 0x33008,
2281 .enable_mask = BIT(0),
2290 .halt_reg = 0x3300c,
2293 .enable_reg = 0x3300c,
2294 .enable_mask = BIT(0),
2303 .halt_reg = 0x34008,
2305 .hwcg_reg = 0x34008,
2308 .enable_reg = 0x34008,
2309 .enable_mask = BIT(0),
2318 .halt_reg = 0x3400c,
2320 .hwcg_reg = 0x3400c,
2323 .enable_reg = 0x3400c,
2324 .enable_mask = BIT(0),
2333 .halt_reg = 0x34010,
2335 .hwcg_reg = 0x34010,
2338 .enable_reg = 0x34010,
2339 .enable_mask = BIT(0),
2348 .halt_reg = 0x23018,
2351 .enable_reg = 0x4b008,
2361 .halt_reg = 0x2300c,
2364 .enable_reg = 0x4b008,
2374 .halt_reg = 0x2314c,
2377 .enable_reg = 0x4b008,
2392 .halt_reg = 0x23280,
2395 .enable_reg = 0x4b008,
2410 .halt_reg = 0x233b4,
2413 .enable_reg = 0x4b008,
2428 .halt_reg = 0x234e8,
2431 .enable_reg = 0x4b008,
2446 .halt_reg = 0x2361c,
2449 .enable_reg = 0x4b008,
2464 .halt_reg = 0x23750,
2467 .enable_reg = 0x4b008,
2482 .halt_reg = 0x23884,
2485 .enable_reg = 0x4b008,
2500 .halt_reg = 0x239b8,
2503 .enable_reg = 0x4b008,
2518 .halt_reg = 0x24018,
2521 .enable_reg = 0x4b008,
2531 .halt_reg = 0x2400c,
2534 .enable_reg = 0x4b008,
2544 .halt_reg = 0x2414c,
2547 .enable_reg = 0x4b008,
2562 .halt_reg = 0x24280,
2565 .enable_reg = 0x4b008,
2580 .halt_reg = 0x243b4,
2583 .enable_reg = 0x4b008,
2598 .halt_reg = 0x244e8,
2601 .enable_reg = 0x4b008,
2616 .halt_reg = 0x2461c,
2619 .enable_reg = 0x4b008,
2634 .halt_reg = 0x24750,
2637 .enable_reg = 0x4b008,
2652 .halt_reg = 0x24884,
2655 .enable_reg = 0x4b018,
2670 .halt_reg = 0x249b8,
2673 .enable_reg = 0x4b018,
2688 .halt_reg = 0xc4018,
2691 .enable_reg = 0x4b000,
2701 .halt_reg = 0xc400c,
2704 .enable_reg = 0x4b000,
2714 .halt_reg = 0xc4284,
2717 .enable_reg = 0x4b000,
2732 .halt_reg = 0xc4150,
2735 .enable_reg = 0x4b000,
2750 .halt_reg = 0x23004,
2752 .hwcg_reg = 0x23004,
2755 .enable_reg = 0x4b008,
2765 .halt_reg = 0x23008,
2767 .hwcg_reg = 0x23008,
2770 .enable_reg = 0x4b008,
2780 .halt_reg = 0x24004,
2782 .hwcg_reg = 0x24004,
2785 .enable_reg = 0x4b008,
2795 .halt_reg = 0x24008,
2797 .hwcg_reg = 0x24008,
2800 .enable_reg = 0x4b008,
2810 .halt_reg = 0xc4004,
2812 .hwcg_reg = 0xc4004,
2815 .enable_reg = 0x4b000,
2825 .halt_reg = 0xc4008,
2827 .hwcg_reg = 0xc4008,
2830 .enable_reg = 0x4b000,
2840 .halt_reg = 0x2000c,
2843 .enable_reg = 0x2000c,
2844 .enable_mask = BIT(0),
2853 .halt_reg = 0x20004,
2856 .enable_reg = 0x20004,
2857 .enable_mask = BIT(0),
2871 .halt_reg = 0x20044,
2873 .hwcg_reg = 0x20044,
2876 .enable_reg = 0x20044,
2877 .enable_mask = BIT(0),
2891 .halt_reg = 0x97034,
2894 .enable_reg = 0x97034,
2895 .enable_mask = BIT(0),
2904 .halt_reg = 0x83020,
2906 .hwcg_reg = 0x83020,
2909 .enable_reg = 0x83020,
2910 .enable_mask = BIT(0),
2919 .halt_reg = 0x83018,
2921 .hwcg_reg = 0x83018,
2924 .enable_reg = 0x83018,
2925 .enable_mask = BIT(0),
2939 .halt_reg = 0x8306c,
2941 .hwcg_reg = 0x8306c,
2944 .enable_reg = 0x8306c,
2945 .enable_mask = BIT(0),
2959 .halt_reg = 0x830a4,
2961 .hwcg_reg = 0x830a4,
2964 .enable_reg = 0x830a4,
2965 .enable_mask = BIT(0),
2979 .halt_reg = 0x83028,
2982 .enable_reg = 0x83028,
2983 .enable_mask = BIT(0),
2997 .halt_reg = 0x830c0,
3000 .enable_reg = 0x830c0,
3001 .enable_mask = BIT(0),
3015 .halt_reg = 0x83024,
3018 .enable_reg = 0x83024,
3019 .enable_mask = BIT(0),
3033 .halt_reg = 0x83064,
3035 .hwcg_reg = 0x83064,
3038 .enable_reg = 0x83064,
3039 .enable_mask = BIT(0),
3053 .halt_reg = 0x1c018,
3056 .enable_reg = 0x1c018,
3057 .enable_mask = BIT(0),
3071 .halt_reg = 0x1c024,
3074 .enable_reg = 0x1c024,
3075 .enable_mask = BIT(0),
3089 .halt_reg = 0x1c020,
3092 .enable_reg = 0x1c020,
3093 .enable_mask = BIT(0),
3102 .halt_reg = 0x1b018,
3105 .enable_reg = 0x1b018,
3106 .enable_mask = BIT(0),
3120 .halt_reg = 0x1b024,
3123 .enable_reg = 0x1b024,
3124 .enable_mask = BIT(0),
3138 .halt_reg = 0x1b020,
3141 .enable_reg = 0x1b020,
3142 .enable_mask = BIT(0),
3151 .halt_reg = 0x1b05c,
3154 .enable_reg = 0x1b05c,
3155 .enable_mask = BIT(0),
3169 .halt_reg = 0x1b060,
3172 .enable_reg = 0x1b060,
3173 .enable_mask = BIT(0),
3187 .halt_reg = 0x1b064,
3189 .hwcg_reg = 0x1b064,
3192 .enable_reg = 0x1b064,
3193 .enable_mask = BIT(0),
3207 .halt_reg = 0x97468,
3210 .enable_reg = 0x97468,
3211 .enable_mask = BIT(0),
3220 .halt_reg = 0x34014,
3222 .hwcg_reg = 0x34014,
3225 .enable_reg = 0x34014,
3226 .enable_mask = BIT(0),
3235 .halt_reg = 0x3401c,
3237 .hwcg_reg = 0x3401c,
3240 .enable_reg = 0x3401c,
3241 .enable_mask = BIT(0),
3250 .gdscr = 0xb6004,
3251 .en_rest_wait_val = 0x2,
3252 .en_few_wait_val = 0x2,
3253 .clk_dis_wait_val = 0xf,
3262 .gdscr = 0xa9004,
3263 .collapse_ctrl = 0x4b104,
3264 .collapse_mask = BIT(0),
3265 .en_rest_wait_val = 0x2,
3266 .en_few_wait_val = 0x2,
3267 .clk_dis_wait_val = 0xf,
3276 .gdscr = 0x77004,
3277 .collapse_ctrl = 0x4b104,
3279 .en_rest_wait_val = 0x2,
3280 .en_few_wait_val = 0x2,
3281 .clk_dis_wait_val = 0xf,
3290 .gdscr = 0x83004,
3291 .en_rest_wait_val = 0x2,
3292 .en_few_wait_val = 0x2,
3293 .clk_dis_wait_val = 0xf,
3302 .gdscr = 0x1c004,
3303 .en_rest_wait_val = 0x2,
3304 .en_few_wait_val = 0x2,
3305 .clk_dis_wait_val = 0xf,
3314 .gdscr = 0x1b004,
3315 .en_rest_wait_val = 0x2,
3316 .en_few_wait_val = 0x2,
3317 .clk_dis_wait_val = 0xf,
3515 [GCC_EMAC0_BCR] = { 0xb6000 },
3516 [GCC_PCIE_0_BCR] = { 0xa9000 },
3517 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
3518 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
3519 [GCC_PCIE_0_PHY_BCR] = { 0xa9144 },
3520 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
3521 [GCC_PCIE_1_BCR] = { 0x77000 },
3522 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
3523 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
3524 [GCC_PCIE_1_PHY_BCR] = { 0xae08c },
3525 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
3526 [GCC_SDCC1_BCR] = { 0x20000 },
3527 [GCC_UFS_PHY_BCR] = { 0x83000 },
3528 [GCC_USB20_PRIM_BCR] = { 0x1c000 },
3529 [GCC_USB2_PHY_PRIM_BCR] = { 0x5c01c },
3530 [GCC_USB2_PHY_SEC_BCR] = { 0x5c020 },
3531 [GCC_USB30_PRIM_BCR] = { 0x1b000 },
3532 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
3533 [GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
3534 [GCC_USB3_PHY_TERT_BCR] = { 0x5c024 },
3535 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c00c },
3536 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c010 },
3537 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
3538 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c014 },
3539 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c018 },
3540 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
3541 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
3542 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
3543 [GCC_VIDEO_BCR] = { 0x34000 },
3570 .max_register = 0x472cffc,
3605 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ in gcc_qcs8300_probe()
3606 qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ in gcc_qcs8300_probe()
3607 qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ in gcc_qcs8300_probe()
3608 qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ in gcc_qcs8300_probe()
3609 qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_qcs8300_probe()
3610 qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ in gcc_qcs8300_probe()
3611 qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ in gcc_qcs8300_probe()