Lines Matching +full:0 +full:x12010
45 .offset = 0x0,
48 .enable_reg = 0x52000,
49 .enable_mask = BIT(0),
76 .offset = 0x3000,
79 .enable_reg = 0x52000,
107 .offset = 0x76000,
110 .enable_reg = 0x52000,
124 .offset = 0x13000,
127 .enable_reg = 0x52000,
141 { 0x1, 2 },
146 .offset = 0x13000,
163 .offset = 0x1a000,
166 .enable_reg = 0x52000,
180 .offset = 0x1b000,
183 .enable_reg = 0x52000,
197 { 0x1, 2 },
202 .offset = 0x1b000,
219 { P_BI_TCXO, 0 },
237 { P_BI_TCXO, 0 },
251 { P_BI_TCXO, 0 },
265 { P_BI_TCXO, 0 },
275 { P_BI_TCXO, 0 },
283 { P_BI_TCXO, 0 },
299 { P_BI_TCXO, 0 },
313 { P_BI_TCXO, 0 },
327 { P_BI_TCXO, 0 },
343 { P_BI_TCXO, 0 },
355 F(19200000, P_BI_TCXO, 1, 0, 0),
360 .cmd_rcgr = 0x48014,
361 .mnd_width = 0,
374 F(19200000, P_BI_TCXO, 1, 0, 0),
375 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
376 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
377 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
378 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
383 .cmd_rcgr = 0x6038,
384 .mnd_width = 0,
399 F(19200000, P_BI_TCXO, 1, 0, 0),
400 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
401 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
402 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
403 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
404 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
409 .cmd_rcgr = 0x601c,
423 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
424 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
425 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
426 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
431 .cmd_rcgr = 0x64004,
445 .cmd_rcgr = 0x65004,
459 .cmd_rcgr = 0x66004,
473 F(9600000, P_BI_TCXO, 2, 0, 0),
474 F(19200000, P_BI_TCXO, 1, 0, 0),
479 .cmd_rcgr = 0x6b02c,
493 F(19200000, P_BI_TCXO, 1, 0, 0),
494 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
499 .cmd_rcgr = 0x6f014,
500 .mnd_width = 0,
513 F(19200000, P_BI_TCXO, 1, 0, 0),
514 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
519 .cmd_rcgr = 0x33010,
520 .mnd_width = 0,
533 F(60000000, P_GPLL0_OUT_AUX2_DIV, 5, 0, 0),
534 F(133250000, P_GPLL3_OUT_MAIN_DIV, 4, 0, 0),
535 F(266500000, P_GPLL3_OUT_MAIN_DIV, 2, 0, 0),
540 .cmd_rcgr = 0x4b008,
541 .mnd_width = 0,
556 F(19200000, P_BI_TCXO, 1, 0, 0),
561 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
564 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
568 F(120000000, P_GPLL0_OUT_AUX2_DIV, 2.5, 0, 0),
569 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
581 .cmd_rcgr = 0x17148,
597 .cmd_rcgr = 0x17278,
613 .cmd_rcgr = 0x173a8,
629 .cmd_rcgr = 0x174d8,
645 .cmd_rcgr = 0x17608,
661 .cmd_rcgr = 0x17738,
677 .cmd_rcgr = 0x18148,
693 .cmd_rcgr = 0x18278,
709 .cmd_rcgr = 0x183a8,
725 .cmd_rcgr = 0x184d8,
741 .cmd_rcgr = 0x18608,
757 .cmd_rcgr = 0x18738,
770 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
771 F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0),
772 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
773 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
778 .cmd_rcgr = 0x12028,
792 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
793 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
794 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
795 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
800 .cmd_rcgr = 0x12010,
801 .mnd_width = 0,
815 F(19200000, P_BI_TCXO, 1, 0, 0),
816 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
817 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
818 F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0),
819 F(202000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
824 .cmd_rcgr = 0x1400c,
838 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
839 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
840 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
841 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
842 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
847 .cmd_rcgr = 0x77020,
861 F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0),
862 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
863 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
864 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
869 .cmd_rcgr = 0x77048,
870 .mnd_width = 0,
883 .cmd_rcgr = 0x7707c,
884 .mnd_width = 0,
897 F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0),
898 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
899 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
904 .cmd_rcgr = 0x77060,
905 .mnd_width = 0,
918 F(19200000, P_BI_TCXO, 1, 0, 0),
919 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
920 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
925 .cmd_rcgr = 0xa601c,
939 .cmd_rcgr = 0xa6034,
940 .mnd_width = 0,
953 F(19200000, P_BI_TCXO, 1, 0, 0),
958 .cmd_rcgr = 0xa6060,
959 .mnd_width = 0,
972 F(66666667, P_GPLL0_OUT_AUX2_DIV, 4.5, 0, 0),
973 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
974 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
975 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
980 .cmd_rcgr = 0xf01c,
994 F(19200000, P_BI_TCXO, 1, 0, 0),
995 F(20000000, P_GPLL0_OUT_AUX2_DIV, 15, 0, 0),
996 F(40000000, P_GPLL0_OUT_AUX2_DIV, 7.5, 0, 0),
997 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1002 .cmd_rcgr = 0xf034,
1003 .mnd_width = 0,
1016 .cmd_rcgr = 0xf060,
1017 .mnd_width = 0,
1030 F(19200000, P_BI_TCXO, 1, 0, 0),
1031 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
1036 .cmd_rcgr = 0x7a018,
1037 .mnd_width = 0,
1050 .halt_reg = 0x770c0,
1052 .hwcg_reg = 0x770c0,
1055 .enable_reg = 0x770c0,
1056 .enable_mask = BIT(0),
1070 .halt_reg = 0xa6084,
1073 .enable_reg = 0xa6084,
1074 .enable_mask = BIT(0),
1088 .halt_reg = 0xf07c,
1091 .enable_reg = 0xf07c,
1092 .enable_mask = BIT(0),
1106 .halt_reg = 0x6a008,
1108 .hwcg_reg = 0x6a008,
1111 .enable_reg = 0x6a008,
1112 .enable_mask = BIT(0),
1121 .halt_reg = 0x6a004,
1123 .hwcg_reg = 0x6a004,
1126 .enable_reg = 0x6a004,
1127 .enable_mask = BIT(0),
1136 .halt_reg = 0x38004,
1138 .hwcg_reg = 0x38004,
1141 .enable_reg = 0x52004,
1151 .halt_reg = 0xb030,
1154 .enable_reg = 0xb030,
1155 .enable_mask = BIT(0),
1164 .halt_reg = 0x4100c,
1166 .hwcg_reg = 0x4100c,
1169 .enable_reg = 0x52004,
1179 .halt_reg = 0x41008,
1182 .enable_reg = 0x52004,
1192 .halt_reg = 0x41004,
1195 .enable_reg = 0x52004,
1205 .halt_reg = 0xa609c,
1208 .enable_reg = 0xa609c,
1209 .enable_mask = BIT(0),
1223 .halt_reg = 0xf078,
1226 .enable_reg = 0xf078,
1227 .enable_mask = BIT(0),
1241 .halt_reg = 0x48000,
1244 .enable_reg = 0x52004,
1259 .halt_reg = 0x71154,
1262 .enable_reg = 0x71154,
1263 .enable_mask = BIT(0),
1274 .enable_reg = 0x52004,
1288 .halt_reg = 0xb038,
1291 .enable_reg = 0xb038,
1292 .enable_mask = BIT(0),
1301 .halt_reg = 0x6010,
1304 .enable_reg = 0x6010,
1305 .enable_mask = BIT(0),
1314 .halt_reg = 0x6034,
1317 .enable_reg = 0x6034,
1318 .enable_mask = BIT(0),
1332 .halt_reg = 0x6018,
1335 .enable_reg = 0x6018,
1336 .enable_mask = BIT(0),
1350 .halt_reg = 0x6014,
1352 .hwcg_reg = 0x6014,
1355 .enable_reg = 0x6014,
1356 .enable_mask = BIT(0),
1365 .halt_reg = 0x64000,
1368 .enable_reg = 0x64000,
1369 .enable_mask = BIT(0),
1383 .halt_reg = 0x65000,
1386 .enable_reg = 0x65000,
1387 .enable_mask = BIT(0),
1401 .halt_reg = 0x66000,
1404 .enable_reg = 0x66000,
1405 .enable_mask = BIT(0),
1421 .enable_reg = 0x52004,
1437 .enable_reg = 0x52004,
1451 .halt_reg = 0x8c010,
1454 .enable_reg = 0x8c010,
1455 .enable_mask = BIT(0),
1464 .halt_reg = 0x7100c,
1467 .enable_reg = 0x7100c,
1468 .enable_mask = BIT(0),
1477 .halt_reg = 0x71018,
1480 .enable_reg = 0x71018,
1481 .enable_mask = BIT(0),
1490 .halt_reg = 0x6f02c,
1493 .enable_reg = 0x6f02c,
1494 .enable_mask = BIT(0),
1508 .halt_reg = 0x6b020,
1511 .enable_reg = 0x5200c,
1526 .halt_reg = 0x6b01c,
1528 .hwcg_reg = 0x6b01c,
1531 .enable_reg = 0x5200c,
1541 .halt_reg = 0x8c00c,
1544 .enable_reg = 0x8c00c,
1545 .enable_mask = BIT(0),
1554 .halt_reg = 0x6b018,
1557 .enable_reg = 0x5200c,
1567 .halt_reg = 0x6b024,
1570 .enable_reg = 0x5200c,
1580 .halt_reg = 0x6b014,
1582 .hwcg_reg = 0x6b014,
1585 .enable_reg = 0x5200c,
1586 .enable_mask = BIT(0),
1595 .halt_reg = 0x6b010,
1598 .enable_reg = 0x5200c,
1608 .halt_reg = 0x6f004,
1611 .enable_reg = 0x6f004,
1612 .enable_mask = BIT(0),
1626 .halt_reg = 0x3300c,
1629 .enable_reg = 0x3300c,
1630 .enable_mask = BIT(0),
1644 .halt_reg = 0x33004,
1646 .hwcg_reg = 0x33004,
1649 .enable_reg = 0x33004,
1650 .enable_mask = BIT(0),
1659 .halt_reg = 0x33008,
1662 .enable_reg = 0x33008,
1663 .enable_mask = BIT(0),
1672 .halt_reg = 0x34004,
1674 .hwcg_reg = 0x34004,
1677 .enable_reg = 0x52004,
1687 .halt_reg = 0xb018,
1689 .hwcg_reg = 0xb018,
1692 .enable_reg = 0xb018,
1693 .enable_mask = BIT(0),
1702 .halt_reg = 0xb020,
1704 .hwcg_reg = 0xb020,
1707 .enable_reg = 0xb020,
1708 .enable_mask = BIT(0),
1717 .halt_reg = 0x6b044,
1719 .hwcg_reg = 0x6b044,
1722 .enable_reg = 0x5200c,
1732 .halt_reg = 0xb014,
1734 .hwcg_reg = 0xb014,
1737 .enable_reg = 0xb014,
1738 .enable_mask = BIT(0),
1747 .halt_reg = 0x4b000,
1750 .enable_reg = 0x4b000,
1751 .enable_mask = BIT(0),
1760 .halt_reg = 0x4b004,
1763 .enable_reg = 0x4b004,
1764 .enable_mask = BIT(0),
1778 .halt_reg = 0x17014,
1781 .enable_reg = 0x5200c,
1791 .halt_reg = 0x1700c,
1794 .enable_reg = 0x5200c,
1804 .halt_reg = 0x17144,
1807 .enable_reg = 0x5200c,
1822 .halt_reg = 0x17274,
1825 .enable_reg = 0x5200c,
1840 .halt_reg = 0x173a4,
1843 .enable_reg = 0x5200c,
1858 .halt_reg = 0x174d4,
1861 .enable_reg = 0x5200c,
1876 .halt_reg = 0x17604,
1879 .enable_reg = 0x5200c,
1894 .halt_reg = 0x17734,
1897 .enable_reg = 0x5200c,
1912 .halt_reg = 0x18014,
1915 .enable_reg = 0x5200c,
1925 .halt_reg = 0x1800c,
1928 .enable_reg = 0x5200c,
1938 .halt_reg = 0x18144,
1941 .enable_reg = 0x5200c,
1956 .halt_reg = 0x18274,
1959 .enable_reg = 0x5200c,
1974 .halt_reg = 0x183a4,
1977 .enable_reg = 0x5200c,
1992 .halt_reg = 0x184d4,
1995 .enable_reg = 0x5200c,
2010 .halt_reg = 0x18604,
2013 .enable_reg = 0x5200c,
2028 .halt_reg = 0x18734,
2031 .enable_reg = 0x5200c,
2046 .halt_reg = 0x17004,
2049 .enable_reg = 0x5200c,
2059 .halt_reg = 0x17008,
2061 .hwcg_reg = 0x17008,
2064 .enable_reg = 0x5200c,
2074 .halt_reg = 0x18004,
2077 .enable_reg = 0x5200c,
2087 .halt_reg = 0x18008,
2089 .hwcg_reg = 0x18008,
2092 .enable_reg = 0x5200c,
2102 .halt_reg = 0x8c030,
2105 .enable_reg = 0x8c030,
2106 .enable_mask = BIT(0),
2115 .halt_reg = 0x8c038,
2118 .enable_reg = 0x8c038,
2119 .enable_mask = BIT(0),
2128 .halt_reg = 0x12008,
2131 .enable_reg = 0x12008,
2132 .enable_mask = BIT(0),
2141 .halt_reg = 0x12004,
2144 .enable_reg = 0x12004,
2145 .enable_mask = BIT(0),
2159 .halt_reg = 0x1200c,
2162 .enable_reg = 0x1200c,
2163 .enable_mask = BIT(0),
2177 .halt_reg = 0x14008,
2180 .enable_reg = 0x14008,
2181 .enable_mask = BIT(0),
2190 .halt_reg = 0x14004,
2193 .enable_reg = 0x14004,
2194 .enable_mask = BIT(0),
2208 .halt_reg = 0x4819c,
2211 .enable_reg = 0x52004,
2212 .enable_mask = BIT(0),
2226 .halt_reg = 0x8c004,
2229 .enable_reg = 0x8c004,
2230 .enable_mask = BIT(0),
2239 .halt_reg = 0x8c000,
2242 .enable_reg = 0x8c000,
2243 .enable_mask = BIT(0),
2252 .halt_reg = 0x77014,
2254 .hwcg_reg = 0x77014,
2257 .enable_reg = 0x77014,
2258 .enable_mask = BIT(0),
2267 .halt_reg = 0x77010,
2269 .hwcg_reg = 0x77010,
2272 .enable_reg = 0x77010,
2273 .enable_mask = BIT(0),
2287 .halt_reg = 0x77044,
2289 .hwcg_reg = 0x77044,
2292 .enable_reg = 0x77044,
2293 .enable_mask = BIT(0),
2307 .halt_reg = 0x77078,
2309 .hwcg_reg = 0x77078,
2312 .enable_reg = 0x77078,
2313 .enable_mask = BIT(0),
2327 .halt_reg = 0x7701c,
2330 .enable_reg = 0x7701c,
2331 .enable_mask = BIT(0),
2340 .halt_reg = 0x77018,
2343 .enable_reg = 0x77018,
2344 .enable_mask = BIT(0),
2353 .halt_reg = 0x77040,
2355 .hwcg_reg = 0x77040,
2358 .enable_reg = 0x77040,
2359 .enable_mask = BIT(0),
2373 .halt_reg = 0xa6010,
2376 .enable_reg = 0xa6010,
2377 .enable_mask = BIT(0),
2391 .halt_reg = 0xa6018,
2394 .enable_reg = 0xa6018,
2395 .enable_mask = BIT(0),
2409 .halt_reg = 0xa6014,
2412 .enable_reg = 0xa6014,
2413 .enable_mask = BIT(0),
2422 .halt_reg = 0x8c028,
2425 .enable_reg = 0x8c028,
2426 .enable_mask = BIT(0),
2435 .halt_reg = 0x8c018,
2438 .enable_reg = 0x8c018,
2439 .enable_mask = BIT(0),
2448 .halt_reg = 0xa6050,
2451 .enable_reg = 0xa6050,
2452 .enable_mask = BIT(0),
2466 .halt_reg = 0xa6054,
2469 .enable_reg = 0xa6054,
2470 .enable_mask = BIT(0),
2484 .halt_reg = 0xa6058,
2487 .enable_reg = 0xa6058,
2488 .enable_mask = BIT(0),
2497 .halt_reg = 0xf010,
2500 .enable_reg = 0xf010,
2501 .enable_mask = BIT(0),
2515 .halt_reg = 0xf018,
2518 .enable_reg = 0xf018,
2519 .enable_mask = BIT(0),
2533 .halt_reg = 0xf014,
2536 .enable_reg = 0xf014,
2537 .enable_mask = BIT(0),
2546 .halt_reg = 0x8c014,
2549 .enable_reg = 0x8c014,
2550 .enable_mask = BIT(0),
2559 .halt_reg = 0xf050,
2562 .enable_reg = 0xf050,
2563 .enable_mask = BIT(0),
2577 .halt_reg = 0xf054,
2580 .enable_reg = 0xf054,
2581 .enable_mask = BIT(0),
2595 .halt_reg = 0xf058,
2598 .enable_reg = 0xf058,
2599 .enable_mask = BIT(0),
2608 .halt_reg = 0x8c008,
2611 .enable_reg = 0x8c008,
2612 .enable_mask = BIT(0),
2621 .halt_reg = 0xb024,
2624 .enable_reg = 0xb024,
2625 .enable_mask = BIT(0),
2639 .gdscr = 0x6004,
2640 .en_rest_wait_val = 0x2,
2641 .en_few_wait_val = 0x2,
2642 .clk_dis_wait_val = 0x2,
2650 .gdscr = 0x6b004,
2651 .en_rest_wait_val = 0x2,
2652 .en_few_wait_val = 0x2,
2653 .clk_dis_wait_val = 0x2,
2661 .gdscr = 0x77004,
2662 .en_rest_wait_val = 0x2,
2663 .en_few_wait_val = 0x2,
2664 .clk_dis_wait_val = 0x2,
2672 .gdscr = 0xa6004,
2673 .en_rest_wait_val = 0x2,
2674 .en_few_wait_val = 0x2,
2675 .clk_dis_wait_val = 0x2,
2683 .gdscr = 0xf004,
2684 .en_rest_wait_val = 0x2,
2685 .en_few_wait_val = 0x2,
2686 .clk_dis_wait_val = 0x2,
2694 .gdscr = 0x7d040,
2703 .gdscr = 0x7d044,
2712 .gdscr = 0x7d048,
2721 .gdscr = 0x7d04c,
2730 .gdscr = 0x7d050,
2739 .gdscr = 0x7d054,
2748 .gdscr = 0x7d058,
2920 [GCC_EMAC_BCR] = { 0x6000 },
2921 [GCC_QUSB2PHY_PRIM_BCR] = { 0xd000 },
2922 [GCC_QUSB2PHY_SEC_BCR] = { 0xd004 },
2923 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2924 [GCC_USB2_PHY_SEC_BCR] = { 0x50018 },
2925 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
2926 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
2927 [GCC_PCIE_0_BCR] = { 0x6b000 },
2928 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
2929 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
2930 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
2931 [GCC_UFS_PHY_BCR] = { 0x77000 },
2932 [GCC_USB20_SEC_BCR] = { 0xa6000 },
2933 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x50008 },
2934 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
2935 [GCC_SDCC1_BCR] = { 0x12000 },
2936 [GCC_SDCC2_BCR] = { 0x14000 },
2958 .max_register = 0xa609c,
2992 regmap_update_bits(regmap, 0x0b084, BIT(0), BIT(0)); in gcc_qcs615_probe()
2993 regmap_update_bits(regmap, 0x9b000, BIT(0), BIT(0)); in gcc_qcs615_probe()
2996 qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ in gcc_qcs615_probe()
2997 qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ in gcc_qcs615_probe()
2998 qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ in gcc_qcs615_probe()
2999 qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ in gcc_qcs615_probe()
3000 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_qcs615_probe()
3001 qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ in gcc_qcs615_probe()
3002 qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ in gcc_qcs615_probe()
3003 qcom_branch_set_clk_en(regmap, 0x480040); /* GCC_CPUSS_GNOC_CLK */ in gcc_qcs615_probe()