Lines Matching +full:0 +full:x3d00
33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
64 .n_reg = 0x316c,
65 .config_reg = 0x3174,
66 .mode_reg = 0x3160,
67 .status_reg = 0x3178,
78 .enable_reg = 0x34c0,
91 .l_reg = 0x3144,
92 .m_reg = 0x3148,
93 .n_reg = 0x314c,
94 .config_reg = 0x3154,
95 .mode_reg = 0x3140,
96 .status_reg = 0x3158,
107 .enable_reg = 0x34c0,
120 .mode_reg = 0x3200,
121 .l_reg = 0x3208,
122 .m_reg = 0x320c,
123 .n_reg = 0x3210,
124 .config_reg = 0x3204,
125 .status_reg = 0x321c,
126 .config_val = 0x7845c665,
127 .droop_reg = 0x3214,
128 .droop_val = 0x0108c000,
146 .mode_reg = 0x3240,
147 .l_reg = 0x3248,
148 .m_reg = 0x324c,
149 .n_reg = 0x3250,
150 .config_reg = 0x3244,
151 .status_reg = 0x325c,
152 .config_val = 0x7845c665,
153 .droop_reg = 0x3314,
154 .droop_val = 0x0108c000,
172 .mode_reg = 0x3300,
173 .l_reg = 0x3308,
174 .m_reg = 0x330c,
175 .n_reg = 0x3310,
176 .config_reg = 0x3304,
177 .status_reg = 0x331c,
178 .config_val = 0x7845c665,
179 .droop_reg = 0x3314,
180 .droop_val = 0x0108c000,
198 .l_reg = 0x31c4,
199 .m_reg = 0x31c8,
200 .n_reg = 0x31cc,
201 .config_reg = 0x31d4,
202 .mode_reg = 0x31c0,
203 .status_reg = 0x31d8,
214 .enable_reg = 0x34c0,
236 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
237 NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
238 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
239 NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
243 .l_reg = 0x31a4,
244 .m_reg = 0x31a8,
245 .n_reg = 0x31ac,
246 .config_reg = 0x31b4,
247 .mode_reg = 0x31a0,
248 .status_reg = 0x31b8,
262 .l_reg = 0x3184,
263 .m_reg = 0x3188,
264 .n_reg = 0x318c,
265 .config_reg = 0x3194,
266 .mode_reg = 0x3180,
267 .status_reg = 0x3198,
291 { P_PXO, 0 },
301 { P_PXO, 0 },
313 { P_PXO, 0 },
318 { P_PXO, 0 },
328 { P_PXO, 0 },
340 { P_PXO, 0 },
356 { P_PXO, 0 },
375 { P_PXO, 0 },
412 .ns_reg = 0x29d4,
413 .md_reg = 0x29d0,
427 .src_sel_shift = 0,
432 .enable_reg = 0x29d4,
445 .halt_reg = 0x2fcc,
448 .enable_reg = 0x29d4,
463 .ns_reg = 0x29f4,
464 .md_reg = 0x29f0,
478 .src_sel_shift = 0,
483 .enable_reg = 0x29f4,
496 .halt_reg = 0x2fcc,
499 .enable_reg = 0x29f4,
514 .ns_reg = 0x2a34,
515 .md_reg = 0x2a30,
529 .src_sel_shift = 0,
534 .enable_reg = 0x2a34,
547 .halt_reg = 0x2fd0,
550 .enable_reg = 0x2a34,
565 .ns_reg = 0x2a54,
566 .md_reg = 0x2a50,
580 .src_sel_shift = 0,
585 .enable_reg = 0x2a54,
598 .halt_reg = 0x2fd0,
601 .enable_reg = 0x2a54,
616 .ns_reg = 0x2a74,
617 .md_reg = 0x2a70,
631 .src_sel_shift = 0,
636 .enable_reg = 0x2a74,
649 .halt_reg = 0x2fd0,
652 .enable_reg = 0x2a74,
667 .ns_reg = 0x2a94,
668 .md_reg = 0x2a90,
682 .src_sel_shift = 0,
687 .enable_reg = 0x2a94,
700 .halt_reg = 0x2fd0,
703 .enable_reg = 0x2a94,
723 { 25000000, P_PXO, 1, 0, 0 },
731 .ns_reg = 0x29cc,
732 .md_reg = 0x29c8,
746 .src_sel_shift = 0,
751 .enable_reg = 0x29cc,
764 .halt_reg = 0x2fcc,
767 .enable_reg = 0x29cc,
782 .ns_reg = 0x29ec,
783 .md_reg = 0x29e8,
797 .src_sel_shift = 0,
802 .enable_reg = 0x29ec,
815 .halt_reg = 0x2fcc,
818 .enable_reg = 0x29ec,
833 .ns_reg = 0x2a2c,
834 .md_reg = 0x2a28,
848 .src_sel_shift = 0,
853 .enable_reg = 0x2a2c,
866 .halt_reg = 0x2fd0,
869 .enable_reg = 0x2a2c,
884 .ns_reg = 0x2a4c,
885 .md_reg = 0x2a48,
899 .src_sel_shift = 0,
904 .enable_reg = 0x2a4c,
917 .halt_reg = 0x2fd0,
920 .enable_reg = 0x2a4c,
935 .ns_reg = 0x2a6c,
936 .md_reg = 0x2a68,
950 .src_sel_shift = 0,
955 .enable_reg = 0x2a6c,
968 .halt_reg = 0x2fd0,
971 .enable_reg = 0x2a6c,
986 .ns_reg = 0x2a8c,
987 .md_reg = 0x2a88,
1001 .src_sel_shift = 0,
1006 .enable_reg = 0x2a8c,
1019 .halt_reg = 0x2fd0,
1022 .enable_reg = 0x2a8c,
1037 .hwcg_reg = 0x29c0,
1039 .halt_reg = 0x2fcc,
1042 .enable_reg = 0x29c0,
1052 .hwcg_reg = 0x29e0,
1054 .halt_reg = 0x2fcc,
1057 .enable_reg = 0x29e0,
1067 .hwcg_reg = 0x2a20,
1069 .halt_reg = 0x2fd0,
1072 .enable_reg = 0x2a20,
1083 .hwcg_reg = 0x2a40,
1085 .halt_reg = 0x2fd0,
1088 .enable_reg = 0x2a40,
1098 .hwcg_reg = 0x2a60,
1100 .halt_reg = 0x2fd0,
1103 .enable_reg = 0x2a60,
1113 .hwcg_reg = 0x2a80,
1115 .halt_reg = 0x2fd0,
1118 .enable_reg = 0x2a80,
1128 { 12500000, P_PXO, 2, 0, 0 },
1129 { 25000000, P_PXO, 1, 0, 0 },
1132 { 96000000, P_PLL8, 4, 0, 0 },
1133 { 128000000, P_PLL8, 3, 0, 0 },
1134 { 192000000, P_PLL8, 2, 0, 0 },
1139 .ns_reg = 0x2d24,
1140 .md_reg = 0x2d00,
1154 .src_sel_shift = 0,
1159 .enable_reg = 0x2d24,
1172 .halt_reg = 0x2fd8,
1175 .enable_reg = 0x2d24,
1190 .ns_reg = 0x2d44,
1191 .md_reg = 0x2d40,
1205 .src_sel_shift = 0,
1210 .enable_reg = 0x2d44,
1223 .halt_reg = 0x2fd8,
1226 .enable_reg = 0x2d44,
1241 .ns_reg = 0x2d64,
1242 .md_reg = 0x2d60,
1256 .src_sel_shift = 0,
1261 .enable_reg = 0x2d64,
1274 .halt_reg = 0x2fd8,
1277 .enable_reg = 0x2d64,
1292 .hwcg_reg = 0x25a0,
1294 .halt_reg = 0x2fc8,
1297 .enable_reg = 0x25a0,
1307 .ns_reg = 0x2e80,
1313 .src_sel_shift = 0,
1317 .enable_reg = 0x2e80,
1329 .halt_reg = 0x2fd8,
1333 .enable_reg = 0x3080,
1356 { 96000000, P_PLL8, 4, 0, 0 },
1357 { 192000000, P_PLL8, 2, 0, 0 },
1362 .ns_reg = 0x282c,
1363 .md_reg = 0x2828,
1377 .src_sel_shift = 0,
1382 .enable_reg = 0x282c,
1394 .halt_reg = 0x2fc8,
1397 .enable_reg = 0x282c,
1412 .ns_reg = 0x286c,
1413 .md_reg = 0x2868,
1427 .src_sel_shift = 0,
1432 .enable_reg = 0x286c,
1444 .halt_reg = 0x2fc8,
1447 .enable_reg = 0x286c,
1462 .hwcg_reg = 0x2820,
1464 .halt_reg = 0x2fc8,
1467 .enable_reg = 0x2820,
1477 .hwcg_reg = 0x2860,
1479 .halt_reg = 0x2fc8,
1482 .enable_reg = 0x2860,
1497 .ns_reg = 0x2710,
1498 .md_reg = 0x270c,
1512 .src_sel_shift = 0,
1517 .enable_reg = 0x2710,
1529 .halt_reg = 0x2fd4,
1532 .enable_reg = 0x2710,
1547 .hwcg_reg = 0x2700,
1549 .halt_reg = 0x2fd4,
1552 .enable_reg = 0x2700,
1562 .hwcg_reg = 0x25c0,
1564 .halt_reg = 0x2fc8,
1567 .enable_reg = 0x25c0,
1577 .halt_reg = 0x2fdc,
1581 .enable_reg = 0x3080,
1591 .hwcg_reg = 0x2208,
1593 .halt_reg = 0x2fdc,
1597 .enable_reg = 0x3080,
1607 .halt_reg = 0x2fd8,
1611 .enable_reg = 0x3080,
1621 .halt_reg = 0x2fd8,
1625 .enable_reg = 0x3080,
1635 .halt_reg = 0x2fd8,
1639 .enable_reg = 0x3080,
1649 .hwcg_reg = 0x27e0,
1651 .halt_reg = 0x2fd8,
1655 .enable_reg = 0x3080,
1665 { 100000000, P_PLL3, 12, 0, 0 },
1670 .ns_reg = 0x3860,
1676 .src_sel_shift = 0,
1681 .enable_reg = 0x3860,
1694 .halt_reg = 0x2fdc,
1697 .enable_reg = 0x3860,
1712 .halt_reg = 0x2fc0,
1715 .enable_reg = 0x22c0,
1725 .halt_reg = 0x2fdc,
1728 .enable_reg = 0x22c8,
1738 .halt_reg = 0x2fd4,
1741 .enable_reg = 0x22cc,
1751 .halt_reg = 0x2fdc,
1754 .enable_reg = 0x22d0,
1764 .ns_reg = 0x3aa0,
1770 .src_sel_shift = 0,
1775 .enable_reg = 0x3aa0,
1788 .halt_reg = 0x2fdc,
1791 .enable_reg = 0x3aa0,
1806 .halt_reg = 0x2fc0,
1809 .enable_reg = 0x3a80,
1819 .halt_reg = 0x2fdc,
1822 .enable_reg = 0x3a88,
1832 .halt_reg = 0x2fd4,
1835 .enable_reg = 0x3a8c,
1845 .halt_reg = 0x2fdc,
1848 .enable_reg = 0x3a90,
1858 .ns_reg = 0x3ae0,
1864 .src_sel_shift = 0,
1869 .enable_reg = 0x3ae0,
1882 .halt_reg = 0x2fdc,
1885 .enable_reg = 0x3ae0,
1900 .halt_reg = 0x2fc0,
1903 .enable_reg = 0x3ac0,
1913 .halt_reg = 0x2fdc,
1916 .enable_reg = 0x3ac8,
1926 .halt_reg = 0x2fd4,
1929 .enable_reg = 0x3acc,
1939 .halt_reg = 0x2fdc,
1942 .enable_reg = 0x3ad0,
1952 { 100000000, P_PLL3, 12, 0, 0 },
1957 .ns_reg = 0x2c08,
1963 .src_sel_shift = 0,
1968 .enable_reg = 0x2c08,
1981 .halt_reg = 0x2fdc,
1984 .enable_reg = 0x2c0c,
1999 .halt_reg = 0x2fdc,
2002 .enable_reg = 0x2c10,
2017 .halt_reg = 0x2fdc,
2020 .enable_reg = 0x2c14,
2032 .halt_reg = 0x2fc0,
2035 .enable_reg = 0x2c20,
2045 .halt_reg = 0x2fdc,
2048 .enable_reg = 0x2c00,
2058 .halt_reg = 0x2fc4,
2061 .enable_reg = 0x2480,
2071 .halt_reg = 0x2fcc,
2074 .enable_reg = 0x2c40,
2089 .ns_reg = 0x3b2c,
2090 .md_reg = 0x3b28,
2104 .src_sel_shift = 0,
2109 .enable_reg = 0x3b2c,
2122 .halt_reg = 0x2fc4,
2125 .enable_reg = 0x3b24,
2140 .halt_reg = 0x2fc4,
2143 .enable_reg = 0x3b34,
2163 .ns_reg = 0x3b44,
2164 .md_reg = 0x3b40,
2178 .src_sel_shift = 0,
2183 .enable_reg = 0x3b44,
2196 .halt_reg = 0x2fc4,
2199 .enable_reg = 0x3b48,
2214 .halt_reg = 0x2fc4,
2217 .enable_reg = 0x3b4c,
2237 .ns_reg = 0x290C,
2238 .md_reg = 0x2908,
2252 .src_sel_shift = 0,
2257 .enable_reg = 0x2968,
2270 .halt_reg = 0x2fcc,
2273 .enable_reg = 0x290c,
2288 .hwcg_reg = 0x2900,
2290 .halt_reg = 0x2fc8,
2293 .enable_reg = 0x2900,
2303 .ns_reg = 0x2968,
2304 .md_reg = 0x2964,
2318 .src_sel_shift = 0,
2323 .enable_reg = 0x2968,
2336 .halt_reg = 0x2fcc,
2339 .enable_reg = 0x2968,
2354 .halt_reg = 0x2fcc,
2357 .enable_reg = 0x296c,
2372 .halt_reg = 0x2fcc,
2375 .enable_reg = 0x2960,
2385 .hwcg_reg = 0x3b00,
2387 .halt_reg = 0x2fcc,
2390 .enable_reg = 0x3b00,
2400 .halt_reg = 0x2fcc,
2401 .halt_bit = 0,
2403 .enable_reg = 0x3b00,
2419 .ns_reg[0] = 0x3cac,
2420 .ns_reg[1] = 0x3cb0,
2421 .md_reg[0] = 0x3ca4,
2422 .md_reg[1] = 0x3ca8,
2423 .bank_reg = 0x3ca0,
2424 .mn[0] = {
2440 .s[0] = {
2441 .src_sel_shift = 0,
2445 .src_sel_shift = 0,
2448 .p[0] = {
2456 .mux_sel_bit = 0,
2459 .enable_reg = 0x3ca0,
2471 .halt_reg = 0x3c20,
2473 .hwcg_reg = 0x3cb4,
2476 .enable_reg = 0x3cb4,
2491 .ns_reg[0] = 0x3ccc,
2492 .ns_reg[1] = 0x3cd0,
2493 .md_reg[0] = 0x3cc4,
2494 .md_reg[1] = 0x3cc8,
2495 .bank_reg = 0x3ca0,
2496 .mn[0] = {
2512 .s[0] = {
2513 .src_sel_shift = 0,
2517 .src_sel_shift = 0,
2520 .p[0] = {
2528 .mux_sel_bit = 0,
2531 .enable_reg = 0x3cc0,
2543 .halt_reg = 0x3c20,
2545 .hwcg_reg = 0x3cd4,
2548 .enable_reg = 0x3cd4,
2563 .ns_reg[0] = 0x3cec,
2564 .ns_reg[1] = 0x3cf0,
2565 .md_reg[0] = 0x3ce4,
2566 .md_reg[1] = 0x3ce8,
2567 .bank_reg = 0x3ce0,
2568 .mn[0] = {
2584 .s[0] = {
2585 .src_sel_shift = 0,
2589 .src_sel_shift = 0,
2592 .p[0] = {
2600 .mux_sel_bit = 0,
2603 .enable_reg = 0x3ce0,
2615 .halt_reg = 0x3c20,
2617 .hwcg_reg = 0x3cf4,
2620 .enable_reg = 0x3cf4,
2635 .ns_reg[0] = 0x3d0c,
2636 .ns_reg[1] = 0x3d10,
2637 .md_reg[0] = 0x3d04,
2638 .md_reg[1] = 0x3d08,
2639 .bank_reg = 0x3d00,
2640 .mn[0] = {
2656 .s[0] = {
2657 .src_sel_shift = 0,
2661 .src_sel_shift = 0,
2664 .p[0] = {
2672 .mux_sel_bit = 0,
2675 .enable_reg = 0x3d00,
2687 .halt_reg = 0x3c20,
2689 .hwcg_reg = 0x3d14,
2692 .enable_reg = 0x3d14,
2707 { 266000000, P_PLL0, 3, 0, 0 },
2708 { 400000000, P_PLL0, 2, 0, 0 },
2713 .ns_reg[0] = 0x3dc4,
2714 .ns_reg[1] = 0x3dc8,
2715 .bank_reg = 0x3dc0,
2716 .s[0] = {
2717 .src_sel_shift = 0,
2721 .src_sel_shift = 0,
2724 .p[0] = {
2732 .mux_sel_bit = 0,
2735 .enable_reg = 0x3dc0,
2747 .halt_reg = 0x3c20,
2750 .enable_reg = 0x3dd0,
2766 { 275000000, P_PLL18, 2, 0, 0 },
2767 { 550000000, P_PLL18, 1, 0, 0 },
2768 { 733000000, P_PLL18, 1, 0, 0 },
2774 { 275000000, P_PLL18, 2, 0, 0 },
2775 { 600000000, P_PLL18, 1, 0, 0 },
2776 { 800000000, P_PLL18, 1, 0, 0 },
2781 .ns_reg[0] = 0x3d2c,
2782 .ns_reg[1] = 0x3d30,
2783 .md_reg[0] = 0x3d24,
2784 .md_reg[1] = 0x3d28,
2785 .bank_reg = 0x3d20,
2786 .mn[0] = {
2802 .s[0] = {
2803 .src_sel_shift = 0,
2807 .src_sel_shift = 0,
2810 .p[0] = {
2818 .mux_sel_bit = 0,
2821 .enable_reg = 0x3d20,
2834 .ns_reg[0] = 0x3d4c,
2835 .ns_reg[1] = 0x3d50,
2836 .md_reg[0] = 0x3d44,
2837 .md_reg[1] = 0x3d48,
2838 .bank_reg = 0x3d40,
2839 .mn[0] = {
2855 .s[0] = {
2856 .src_sel_shift = 0,
2860 .src_sel_shift = 0,
2863 .p[0] = {
2871 .mux_sel_bit = 0,
2874 .enable_reg = 0x3d40,
2893 .ns_reg[0] = 0x36C4,
2894 .ns_reg[1] = 0x36C8,
2895 .bank_reg = 0x36C0,
2896 .s[0] = {
2897 .src_sel_shift = 0,
2901 .src_sel_shift = 0,
2904 .p[0] = {
2912 .mux_sel_bit = 0,
2915 .enable_reg = 0x36C0,
2927 .halt_reg = 0x2FDC,
2929 .hwcg_reg = 0x36CC,
2932 .enable_reg = 0x36CC,
2953 .ns_reg[0] = 0x3d84,
2954 .ns_reg[1] = 0x3d88,
2955 .bank_reg = 0x3d80,
2956 .s[0] = {
2957 .src_sel_shift = 0,
2961 .src_sel_shift = 0,
2964 .p[0] = {
2972 .mux_sel_bit = 0,
2975 .enable_reg = 0x3d80,
2987 .halt_reg = 0x3c20,
2989 .hwcg_reg = 0x3d8c,
2992 .enable_reg = 0x3d8c,
3013 .ns_reg[0] = 0x3c64,
3014 .ns_reg[1] = 0x3c68,
3015 .bank_reg = 0x3c60,
3016 .s[0] = {
3017 .src_sel_shift = 0,
3021 .src_sel_shift = 0,
3024 .p[0] = {
3032 .mux_sel_bit = 0,
3035 .enable_reg = 0x3c60,
3047 .halt_reg = 0x3c20,
3049 .hwcg_reg = 0x3c6c,
3052 .enable_reg = 0x3c6c,
3197 [QDSS_STM_RESET] = { 0x2060, 6 },
3198 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3199 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3200 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
3201 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3202 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
3203 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3204 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3205 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3206 [ADM0_C2_RESET] = { 0x220c, 4 },
3207 [ADM0_C1_RESET] = { 0x220c, 3 },
3208 [ADM0_C0_RESET] = { 0x220c, 2 },
3209 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3210 [ADM0_RESET] = { 0x220c, 0 },
3211 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3212 [QDSS_POR_RESET] = { 0x2260, 4 },
3213 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3214 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3215 [QDSS_AXI_RESET] = { 0x2260, 1 },
3216 [QDSS_DBG_RESET] = { 0x2260, 0 },
3217 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3218 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
3219 [PCIE_EXT_RESET] = { 0x22dc, 6 },
3220 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3221 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3222 [PCIE_POR_RESET] = { 0x22dc, 3 },
3223 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3224 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
3225 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3226 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3227 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3228 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3229 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3230 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3231 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3232 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3233 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3234 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3235 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3236 [PPSS_PROC_RESET] = { 0x2594, 1 },
3237 [PPSS_RESET] = { 0x2594, 0 },
3238 [DMA_BAM_RESET] = { 0x25c0, 7 },
3239 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3240 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3241 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3242 [TSIF_H_RESET] = { 0x2700, 7 },
3243 [CE1_H_RESET] = { 0x2720, 7 },
3244 [CE1_CORE_RESET] = { 0x2724, 7 },
3245 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3246 [CE2_H_RESET] = { 0x2740, 7 },
3247 [CE2_CORE_RESET] = { 0x2744, 7 },
3248 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3249 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3250 [RPM_PROC_RESET] = { 0x27c0, 7 },
3251 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3252 [SDC1_RESET] = { 0x2830, 0 },
3253 [SDC2_RESET] = { 0x2850, 0 },
3254 [SDC3_RESET] = { 0x2870, 0 },
3255 [SDC4_RESET] = { 0x2890, 0 },
3256 [USB_HS1_RESET] = { 0x2910, 0 },
3257 [USB_HSIC_RESET] = { 0x2934, 0 },
3258 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3259 [USB_FS1_RESET] = { 0x2974, 0 },
3260 [GSBI1_RESET] = { 0x29dc, 0 },
3261 [GSBI2_RESET] = { 0x29fc, 0 },
3262 [GSBI3_RESET] = { 0x2a1c, 0 },
3263 [GSBI4_RESET] = { 0x2a3c, 0 },
3264 [GSBI5_RESET] = { 0x2a5c, 0 },
3265 [GSBI6_RESET] = { 0x2a7c, 0 },
3266 [GSBI7_RESET] = { 0x2a9c, 0 },
3267 [SPDM_RESET] = { 0x2b6c, 0 },
3268 [SEC_CTRL_RESET] = { 0x2b80, 7 },
3269 [TLMM_H_RESET] = { 0x2ba0, 7 },
3270 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
3271 [SATA_RESET] = { 0x2c1c, 0 },
3272 [TSSC_RESET] = { 0x2ca0, 7 },
3273 [PDM_RESET] = { 0x2cc0, 12 },
3274 [MPM_H_RESET] = { 0x2da0, 7 },
3275 [MPM_RESET] = { 0x2da4, 0 },
3276 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3277 [PRNG_RESET] = { 0x2e80, 12 },
3278 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3279 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
3280 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3281 [PCIE_1_M_RESET] = { 0x3a98, 1 },
3282 [PCIE_1_S_RESET] = { 0x3a98, 0 },
3283 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
3284 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
3285 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
3286 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
3287 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
3288 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
3289 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
3290 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
3291 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
3292 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
3293 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
3294 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
3295 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
3296 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
3297 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
3298 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
3299 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
3300 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
3301 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
3302 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
3303 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
3304 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
3305 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
3306 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
3307 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
3308 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
3309 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
3310 [NSSFB0_RESET] = { 0x3b60, 6 },
3311 [NSSFB1_RESET] = { 0x3b60, 7 },
3312 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
3313 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
3314 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
3315 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
3316 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
3317 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
3318 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
3319 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
3320 [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
3321 [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
3322 [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
3323 [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
3324 [GMAC_AHB_RESET] = { 0x3e24, 0 },
3325 [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
3326 [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
3327 [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
3328 [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
3329 [CRYPTO_AHB_RESET] = { 0x3e10, 0},
3330 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
3331 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
3332 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
3333 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
3334 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
3335 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
3336 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
3337 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
3338 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
3339 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
3340 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
3341 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
3342 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
3343 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
3344 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
3345 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
3346 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
3347 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
3348 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
3349 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
3350 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
3351 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
3352 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
3353 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
3354 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
3355 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
3356 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
3357 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
3358 [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
3365 .max_register = 0x3e40,
3414 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); in gcc_ipq806x_probe()
3415 regmap_write(regmap, 0x31b0, 0x3080); in gcc_ipq806x_probe()
3418 regmap_write(regmap, 0x3cb8, 8); in gcc_ipq806x_probe()
3419 regmap_write(regmap, 0x3cd8, 8); in gcc_ipq806x_probe()
3420 regmap_write(regmap, 0x3cf8, 8); in gcc_ipq806x_probe()
3421 regmap_write(regmap, 0x3d18, 8); in gcc_ipq806x_probe()