Lines Matching +full:0 +full:x1020
35 { 249600000, 2000000000, 0 },
39 .l = 0x3a,
40 .alpha = 0x5555,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002067,
43 .test_ctl_val = 0x40000000,
44 .test_ctl_hi_val = 0x00000002,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00004805,
50 .offset = 0x0,
67 { P_BI_TCXO, 0 },
79 { P_BI_TCXO, 0 },
89 { P_BI_TCXO, 0 },
103 { P_BI_TCXO, 0 },
113 { P_BI_TCXO, 0 },
123 { P_BI_TCXO, 0 },
131 F(19200000, P_BI_TCXO, 1, 0, 0),
132 F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
133 F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
138 .cmd_rcgr = 0x115c,
139 .mnd_width = 0,
153 .cmd_rcgr = 0x10c4,
154 .mnd_width = 0,
167 .reg = 0x10dc,
168 .shift = 0,
182 F(19200000, P_BI_TCXO, 1, 0, 0),
187 .cmd_rcgr = 0x1144,
188 .mnd_width = 0,
201 F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
202 F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
203 F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
204 F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
209 .cmd_rcgr = 0x1114,
210 .mnd_width = 0,
224 .cmd_rcgr = 0x10f8,
225 .mnd_width = 0,
238 .cmd_rcgr = 0x112c,
252 .cmd_rcgr = 0x10e0,
253 .mnd_width = 0,
266 F(19200000, P_BI_TCXO, 1, 0, 0),
267 F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
268 F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
269 F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
270 F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
271 F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
276 .cmd_rcgr = 0x107c,
277 .mnd_width = 0,
291 .cmd_rcgr = 0x1064,
305 .cmd_rcgr = 0x1094,
306 .mnd_width = 0,
320 .cmd_rcgr = 0x10ac,
321 .mnd_width = 0,
334 .reg = 0x1110,
335 .shift = 0,
349 .halt_reg = 0x104c,
352 .enable_reg = 0x104c,
353 .enable_mask = BIT(0),
367 .halt_reg = 0x102c,
370 .enable_reg = 0x102c,
371 .enable_mask = BIT(0),
385 .halt_reg = 0x1030,
388 .enable_reg = 0x1030,
389 .enable_mask = BIT(0),
403 .halt_reg = 0x1048,
406 .enable_reg = 0x1048,
407 .enable_mask = BIT(0),
421 .halt_reg = 0x1040,
424 .enable_reg = 0x1040,
425 .enable_mask = BIT(0),
439 .halt_reg = 0x1038,
442 .enable_reg = 0x1038,
443 .enable_mask = BIT(0),
457 .halt_reg = 0x103c,
460 .enable_reg = 0x103c,
461 .enable_mask = BIT(0),
475 .halt_reg = 0x1044,
478 .enable_reg = 0x1044,
479 .enable_mask = BIT(0),
493 .halt_reg = 0x1034,
496 .enable_reg = 0x1034,
497 .enable_mask = BIT(0),
511 .halt_reg = 0x1010,
514 .enable_reg = 0x1010,
515 .enable_mask = BIT(0),
529 .halt_reg = 0x1020,
532 .enable_reg = 0x1020,
533 .enable_mask = BIT(0),
547 .halt_reg = 0x2004,
550 .enable_reg = 0x2004,
551 .enable_mask = BIT(0),
565 .halt_reg = 0x100c,
568 .enable_reg = 0x100c,
569 .enable_mask = BIT(0),
583 .halt_reg = 0x1018,
586 .enable_reg = 0x1018,
587 .enable_mask = BIT(0),
601 .halt_reg = 0x200c,
604 .enable_reg = 0x200c,
605 .enable_mask = BIT(0),
619 .halt_reg = 0x2008,
622 .enable_reg = 0x2008,
623 .enable_mask = BIT(0),
637 .halt_reg = 0x1028,
640 .enable_reg = 0x1028,
641 .enable_mask = BIT(0),
655 .halt_reg = 0x5004,
658 .enable_reg = 0x5004,
659 .enable_mask = BIT(0),
668 .halt_reg = 0x5008,
671 .enable_reg = 0x5008,
672 .enable_mask = BIT(0),
682 .gdscr = 0x1004,
735 .max_register = 0x10000,