Lines Matching full:pll
13 #include "clk-alpha-pll.h"
338 /* TRION PLL specific settings and offsets */
342 /* LUCID PLL specific settings and offsets */
345 /* LUCID 5LPE PLL specific settings and offsets */
351 /* LUCID EVO PLL specific settings and offsets */
358 /* PONGO ELU PLL specific setting and offsets */
364 /* ZONDA PLL specific */
381 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
387 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
389 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
395 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
410 #define wait_for_pll_enable_active(pll) \ argument
411 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
413 #define wait_for_pll_enable_lock(pll) \ argument
414 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
416 #define wait_for_zonda_pll_freq_lock(pll) \ argument
417 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
419 #define wait_for_pll_disable(pll) \ argument
420 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
422 #define wait_for_pll_offline(pll) \ argument
423 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
425 #define wait_for_pll_update(pll) \ argument
426 wait_for_pll(pll, PLL_UPDATE, 1, "update")
428 #define wait_for_pll_update_ack_set(pll) \ argument
429 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
431 #define wait_for_pll_update_ack_clear(pll) \ argument
432 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
441 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
446 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
447 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
448 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
450 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
451 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
454 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
455 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
477 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
480 regmap_update_bits(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
484 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
488 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
492 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
495 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
496 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
503 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
506 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
512 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
515 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
522 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
528 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
531 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
535 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
536 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
541 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
547 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
552 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
558 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
561 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
581 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
585 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
594 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
601 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
613 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
618 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
622 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
633 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
636 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
647 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
654 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
692 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
694 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
695 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
709 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
710 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
712 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
714 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
716 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
718 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
733 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
738 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
740 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
741 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
748 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
749 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
750 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
752 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
755 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
759 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
761 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
766 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
770 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
776 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
779 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
780 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
783 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
790 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
792 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
796 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
797 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
798 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
803 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
809 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
811 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
814 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
819 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
822 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
842 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
843 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
848 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
851 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
852 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
857 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_huayra_2290_pll_configure() argument
862 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_huayra_2290_pll_configure()
863 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_huayra_2290_pll_configure()
864 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_huayra_2290_pll_configure()
865 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_huayra_2290_pll_configure()
866 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_huayra_2290_pll_configure()
867 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_huayra_2290_pll_configure()
868 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_huayra_2290_pll_configure()
869 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_huayra_2290_pll_configure()
870 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_huayra_2290_pll_configure()
873 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_huayra_2290_pll_configure()
874 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
879 /* Take PLL out from reset state */ in clk_huayra_2290_pll_configure()
880 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_huayra_2290_pll_configure()
881 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
886 /* Enable PLL output */ in clk_huayra_2290_pll_configure()
887 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_huayra_2290_pll_configure()
942 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
945 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
946 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
949 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
995 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
1000 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
1003 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
1006 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
1016 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
1019 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
1022 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
1023 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
1026 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
1029 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
1043 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
1049 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
1050 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
1059 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
1061 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
1066 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
1067 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
1071 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
1080 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
1084 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
1086 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
1090 /* Enable the PLL outputs */ in clk_trion_pll_enable()
1091 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
1096 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
1097 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
1103 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
1104 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
1108 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
1118 /* Disable the global PLL output */ in clk_trion_pll_disable()
1119 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1123 /* Disable the PLL outputs */ in clk_trion_pll_disable()
1124 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
1129 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
1130 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
1131 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1137 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
1138 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
1140 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
1141 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
1196 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1199 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
1202 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1227 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
1230 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
1236 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1243 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1246 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1249 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1261 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1267 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1268 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1285 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1290 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1291 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1292 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1294 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1296 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1298 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1300 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1302 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1308 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1311 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1312 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1315 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1318 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1325 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1327 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1329 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1338 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1341 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1345 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1349 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1353 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1357 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1362 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1366 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1370 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1375 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1382 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1384 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1386 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1396 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1401 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1405 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1406 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1412 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1413 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1415 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1416 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1443 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1454 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1455 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1457 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1462 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1466 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1471 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1472 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1480 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1482 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1486 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1487 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1500 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1501 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1503 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1506 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1538 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1542 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1546 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1547 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1549 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1550 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1551 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1562 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1563 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1566 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1568 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1569 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1571 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1572 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1573 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1585 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1587 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1588 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1595 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1596 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1600 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1601 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1602 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1607 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1608 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, in clk_trion_pll_postdiv_set_rate()
1609 val << pll->post_div_shift); in clk_trion_pll_postdiv_set_rate()
1622 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1624 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1625 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1631 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1635 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1638 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1646 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1647 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1648 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1653 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1654 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1655 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1666 * clk_trion_pll_configure - configure the trion pll
1668 * @pll: clk alpha pll
1670 * @config: configuration to apply for pll
1672 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1676 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1677 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1679 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1680 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1684 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1685 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1686 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1687 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1689 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1691 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1693 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1695 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1697 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1699 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1701 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1703 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1706 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1709 /* Disable PLL output */ in clk_trion_pll_configure()
1710 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1713 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1715 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1716 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1721 * The TRION PLL requires a power-on self-calibration which happens when the
1722 * PLL comes out of reset. Calibrate in case it is not completed.
1726 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1731 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1756 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1758 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1768 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); in __alpha_pll_trion_set_rate()
1769 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1771 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1772 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1778 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1780 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1785 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1790 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1795 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1835 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1838 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1839 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1840 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1842 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1844 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1846 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1848 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1856 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1857 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1868 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1869 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1872 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1888 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1890 * @pll: clk alpha pll
1892 * @config: configuration to apply for pll
1894 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_5lpe_pll_configure() argument
1898 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_5lpe_pll_configure()
1899 * RCGs that will lock up if we disable the PLL below. in clk_lucid_5lpe_pll_configure()
1901 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_5lpe_pll_configure()
1902 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); in clk_lucid_5lpe_pll_configure()
1906 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_lucid_5lpe_pll_configure()
1907 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_lucid_5lpe_pll_configure()
1908 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_5lpe_pll_configure()
1909 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_lucid_5lpe_pll_configure()
1911 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1913 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1915 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_lucid_5lpe_pll_configure()
1917 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1919 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1921 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_lucid_5lpe_pll_configure()
1923 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1925 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1928 /* Disable PLL output */ in clk_lucid_5lpe_pll_configure()
1929 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_5lpe_pll_configure()
1932 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_5lpe_pll_configure()
1934 /* Place the PLL in STANDBY mode */ in clk_lucid_5lpe_pll_configure()
1935 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_5lpe_pll_configure()
1941 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1945 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1954 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1957 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1958 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) in alpha_pll_lucid_5lpe_enable()
1961 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1965 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1967 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1971 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1972 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1976 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1977 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1982 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
1986 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
1996 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
1997 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
2001 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
2002 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
2006 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
2007 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
2011 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
2012 * when the PLL comes out of reset. Calibrate in case it is not completed.
2016 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
2022 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
2051 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
2052 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
2057 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
2060 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
2067 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
2068 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
2069 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
2074 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
2075 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
2076 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
2081 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2082 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
2083 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2119 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
2122 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
2123 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
2124 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
2125 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
2126 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
2127 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
2128 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
2129 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
2130 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
2131 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
2132 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
2134 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
2136 /* Disable PLL output */ in clk_zonda_pll_configure()
2137 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
2140 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
2142 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
2143 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
2149 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
2150 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
2154 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
2161 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
2164 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
2165 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
2173 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
2176 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
2178 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
2182 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
2184 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
2188 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
2189 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
2191 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
2192 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
2199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
2200 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
2203 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
2211 /* Disable the global PLL output */ in clk_zonda_pll_disable()
2212 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
2214 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
2215 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
2217 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
2218 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2220 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
2221 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
2237 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
2240 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2253 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2254 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2263 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2267 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2269 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2273 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2288 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2294 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_evo_pll_configure()
2295 * RCGs that will lock up if we disable the PLL below. in clk_lucid_evo_pll_configure()
2297 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_evo_pll_configure()
2298 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); in clk_lucid_evo_pll_configure()
2303 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2304 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2305 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2306 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2307 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2308 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2309 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2310 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2311 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2312 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2313 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_evo_pll_configure()
2315 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2316 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2319 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2320 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2324 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_ole_pll_configure() argument
2331 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_ole_pll_configure()
2332 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_ole_pll_configure()
2333 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_ole_pll_configure()
2334 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_ole_pll_configure()
2335 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2336 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_ole_pll_configure()
2337 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_ole_pll_configure()
2338 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_ole_pll_configure()
2339 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_ole_pll_configure()
2340 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2341 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_ole_pll_configure()
2343 /* Disable PLL output */ in clk_lucid_ole_pll_configure()
2344 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_ole_pll_configure()
2347 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_ole_pll_configure()
2348 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_ole_pll_configure()
2354 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2355 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2359 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2368 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2371 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2372 if (trion_pll_is_enabled(pll, regmap)) in alpha_pll_lucid_evo_enable()
2375 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2380 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2382 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2386 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2387 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2391 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2392 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2403 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2404 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2408 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2418 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2419 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2423 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2424 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2428 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2429 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2432 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2437 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2443 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2483 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2484 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2487 regmap_read(regmap, PLL_L_VAL(pll), &l); in alpha_pll_lucid_evo_recalc_rate()
2489 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); in alpha_pll_lucid_evo_recalc_rate()
2491 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2540 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_prepare() local
2541 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_prepare()
2544 /* Enable PLL intially to one-time calibrate against XO. */ in alpha_pll_pongo_elu_prepare()
2545 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_pongo_elu_prepare()
2546 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_pongo_elu_prepare()
2547 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT); in alpha_pll_pongo_elu_prepare()
2550 pll->clkr.regmap = regmap; in alpha_pll_pongo_elu_prepare()
2551 ret = wait_for_pll_enable_lock(pll); in alpha_pll_pongo_elu_prepare()
2553 /* Reverse calibration - disable PLL output */ in alpha_pll_pongo_elu_prepare()
2554 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_pongo_elu_prepare()
2558 /* Disable PLL after one-time calibration. */ in alpha_pll_pongo_elu_prepare()
2559 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_pongo_elu_prepare()
2562 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, in alpha_pll_pongo_elu_prepare()
2570 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_enable() local
2571 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_enable()
2574 /* Check if PLL is already enabled */ in alpha_pll_pongo_elu_enable()
2575 if (trion_pll_is_enabled(pll, regmap)) in alpha_pll_pongo_elu_enable()
2578 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_pongo_elu_enable()
2583 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_pongo_elu_enable()
2585 ret = wait_for_pll_enable_lock(pll); in alpha_pll_pongo_elu_enable()
2589 /* Enable the global PLL outputs */ in alpha_pll_pongo_elu_enable()
2590 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_pongo_elu_enable()
2602 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_disable() local
2603 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_disable()
2606 /* Disable the global PLL output */ in alpha_pll_pongo_elu_disable()
2607 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_pongo_elu_disable()
2611 /* Place the PLL mode in STANDBY */ in alpha_pll_pongo_elu_disable()
2612 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_pongo_elu_disable()
2618 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_recalc_rate() local
2619 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_recalc_rate()
2622 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) in alpha_pll_pongo_elu_recalc_rate()
2627 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); in alpha_pll_pongo_elu_recalc_rate()
2638 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, in clk_pongo_elu_pll_configure() argument
2644 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, in clk_pongo_elu_pll_configure()
2647 if (trion_pll_is_enabled(pll, regmap)) in clk_pongo_elu_pll_configure()
2650 if (regmap_read(regmap, PLL_L_VAL(pll), &val)) in clk_pongo_elu_pll_configure()
2656 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_pongo_elu_pll_configure()
2657 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_pongo_elu_pll_configure()
2658 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_pongo_elu_pll_configure()
2659 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_pongo_elu_pll_configure()
2660 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_pongo_elu_pll_configure()
2661 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val); in clk_pongo_elu_pll_configure()
2662 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_pongo_elu_pll_configure()
2664 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_pongo_elu_pll_configure()
2665 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_pongo_elu_pll_configure()
2666 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_pongo_elu_pll_configure()
2667 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_pongo_elu_pll_configure()
2668 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_pongo_elu_pll_configure()
2669 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val); in clk_pongo_elu_pll_configure()
2671 /* Disable PLL output */ in clk_pongo_elu_pll_configure()
2672 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_pongo_elu_pll_configure()
2676 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2679 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2680 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2681 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2682 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2683 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2684 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2685 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2686 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2688 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2690 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2699 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2702 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_rivian_evo_pll_recalc_rate()
2710 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_round_rate() local
2716 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_rivian_evo_pll_round_rate()
2719 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_round_rate()
2720 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_round_rate()
2734 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_stromer_pll_configure() argument
2739 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_stromer_pll_configure()
2740 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_stromer_pll_configure()
2741 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_stromer_pll_configure()
2743 if (pll_has_64bit_config(pll)) in clk_stromer_pll_configure()
2744 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_stromer_pll_configure()
2747 if (pll_alpha_width(pll) > 32) in clk_stromer_pll_configure()
2748 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_stromer_pll_configure()
2770 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_stromer_pll_configure()
2772 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ in clk_stromer_pll_configure()
2779 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); in clk_stromer_pll_configure()
2780 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_stromer_pll_configure()
2781 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_stromer_pll_configure()
2783 if (pll->flags & SUPPORTS_FSM_MODE) in clk_stromer_pll_configure()
2784 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_stromer_pll_configure()
2803 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_set_rate() local
2810 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_set_rate()
2813 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_set_rate()
2814 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_set_rate()
2817 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_set_rate()
2824 * Stromer PLL supports Dynamic programming. in clk_alpha_pll_stromer_set_rate()
2825 * It allows the PLL frequency to be changed on-the-fly without first in clk_alpha_pll_stromer_set_rate()
2828 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in clk_alpha_pll_stromer_set_rate()
2831 ret = wait_for_pll_update(pll); in clk_alpha_pll_stromer_set_rate()
2835 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_set_rate()
2852 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_plus_set_rate() local
2853 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_stromer_plus_set_rate()
2859 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); in clk_alpha_pll_stromer_plus_set_rate()
2863 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); in clk_alpha_pll_stromer_plus_set_rate()
2868 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_plus_set_rate()
2873 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_plus_set_rate()
2874 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_plus_set_rate()
2877 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_plus_set_rate()
2880 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); in clk_alpha_pll_stromer_plus_set_rate()
2884 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, in clk_alpha_pll_stromer_plus_set_rate()
2890 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_plus_set_rate()
2892 pr_err("Wait for PLL enable lock failed [%s] %d\n", in clk_alpha_pll_stromer_plus_set_rate()
2898 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, in clk_alpha_pll_stromer_plus_set_rate()
2914 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_regera_pll_configure() argument
2917 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_regera_pll_configure()
2918 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_regera_pll_configure()
2919 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_regera_pll_configure()
2920 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_regera_pll_configure()
2921 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_regera_pll_configure()
2922 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_regera_pll_configure()
2923 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_regera_pll_configure()
2924 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_regera_pll_configure()
2925 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_regera_pll_configure()
2926 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_regera_pll_configure()
2927 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_regera_pll_configure()
2930 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_regera_pll_configure()