Lines Matching +full:x1e80100 +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
23 	tristate "X1E80100 Camera Clock Controller"
27 	  Support for the camera clock controller on X1E80100 devices.
31 	tristate "X1E80100 Display Clock Controller"
36 	  Technologies, Inc. X1E80100 devices.
41 	tristate "X1E80100 Global Clock Controller"
46 	  X1E80100 devices.
51 	tristate "X1E80100 Graphics Clock Controller"
55 	  Support for the graphics clock controller on X1E80100 devices.
60 	tristate "X1E80100 TCSR Clock Controller"
64 	  Support for the TCSR clock controller on X1E80100 devices.
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
1287 	  Say Y if you want to toggle LPASS-adjacent resets within
1386 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1388 	  Support for the high-frequency PLLs present on Qualcomm devices.
1395 	  Support for the Krait ACC and GCC clock controllers. Say Y