Lines Matching +full:qdu1000 +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
807 	tristate "QDU1000/QRU1000 Global Clock Controller"
810 	  Support for the global clock controller on QDU1000 and
815 	tristate "QDU1000/QRU1000 ECPRI Clock Controller"
819 	  Support for the ECPRI clock controller on QDU1000 and
1287 	  Say Y if you want to toggle LPASS-adjacent resets within
1386 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1388 	  Support for the high-frequency PLLs present on Qualcomm devices.
1395 	  Support for the Krait ACC and GCC clock controllers. Say Y