Lines Matching +full:gcc +full:- +full:sm8450

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
939 	tristate "SM8450 Camera Clock Controller"
943 	  Support for the camera clock controller on SM8450 or SM8475 devices.
1033 	tristate "SM8450 Display Clock Controller"
1038 	  SM8450 or SM8475 devices.
1145 	tristate "SM8450 Global Clock Controller"
1149 	  Support for the global clock controller on SM8450 or SM8475
1254 	tristate "SM8450 Graphics Clock Controller"
1258 	  Support for the graphics clock controller on SM8450 or SM8475
1287 	  Say Y if you want to toggle LPASS-adjacent resets within
1386 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1388 	  Support for the high-frequency PLLs present on Qualcomm devices.
1395 	  Support for the Krait ACC and GCC clock controllers. Say Y
1415 	tristate "SM8450 Video Clock Controller"
1421 	  SM8450 or SM8475 devices.