Lines Matching +full:gcc +full:- +full:sm6115

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
973 	tristate "SM6115 Display Clock Controller"
978 	  SM6115/SM4250 devices.
1073 	tristate "SM6115 and SM4250 Global Clock Controller"
1077 	  Support for the global clock controller on SM6115 and SM4250 devices.
1191 	tristate "SM6115 Graphics Clock Controller"
1195 	  Support for the graphics clock controller on SM6115 devices.
1282 	tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller"
1286 	  Support for the LPASS clock controller on SM6115 devices.
1287 	  Say Y if you want to toggle LPASS-adjacent resets within
1386 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1388 	  Support for the high-frequency PLLs present on Qualcomm devices.
1395 	  Support for the Krait ACC and GCC clock controllers. Say Y