Lines Matching +full:gcc +full:- +full:sdx55

1 # SPDX-License-Identifier: GPL-2.0-only
94 	tristate "A7 PLL driver for SDX55 and SDX65"
96 	  Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
98 	  Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
121 	tristate "SDX55 and SDX65 APCS Clock Controller"
125 	  Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
128 	  such as SDX55, SDX65.
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
871 	tristate "SDX55 Global Clock Controller"
875 	  Support for the global clock controller on SDX55 devices.
1287 	  Say Y if you want to toggle LPASS-adjacent resets within
1386 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1388 	  Support for the high-frequency PLLs present on Qualcomm devices.
1395 	  Support for the Krait ACC and GCC clock controllers. Say Y