Lines Matching +full:pulse +full:- +full:width

1 // SPDX-License-Identifier: GPL-2.0
9 /* The VCLK gate has a supplementary reset bit to pulse after ungating */
14 	return (struct meson_vclk_gate_data *)clk->data;  in clk_get_meson_vclk_gate_data()
22 	meson_parm_write(clk->map, &vclk->enable, 1);  in meson_vclk_gate_enable()
24 	/* Do a reset pulse */  in meson_vclk_gate_enable()
25 	meson_parm_write(clk->map, &vclk->reset, 1);  in meson_vclk_gate_enable()
26 	meson_parm_write(clk->map, &vclk->reset, 0);  in meson_vclk_gate_enable()
36 	meson_parm_write(clk->map, &vclk->enable, 0);  in meson_vclk_gate_disable()
44 	return meson_parm_read(clk->map, &vclk->enable);  in meson_vclk_gate_is_enabled()
59 	return (struct meson_vclk_div_data *)clk->data;  in clk_get_meson_vclk_div_data()
68 	return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),  in meson_vclk_div_recalc_rate()
69 				   vclk->table, vclk->flags, vclk->div.width);  in meson_vclk_div_recalc_rate()
78 	return divider_determine_rate(hw, req, vclk->table, vclk->div.width,  in meson_vclk_div_determine_rate()
79 				      vclk->flags);  in meson_vclk_div_determine_rate()
89 	ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,  in meson_vclk_div_set_rate()
90 			      vclk->flags);  in meson_vclk_div_set_rate()
94 	meson_parm_write(clk->map, &vclk->div, ret);  in meson_vclk_div_set_rate()
105 	meson_parm_write(clk->map, &vclk->reset, 0);  in meson_vclk_div_enable()
106 	meson_parm_write(clk->map, &vclk->enable, 1);  in meson_vclk_div_enable()
117 	meson_parm_write(clk->map, &vclk->enable, 0);  in meson_vclk_div_disable()
118 	meson_parm_write(clk->map, &vclk->reset, 1);  in meson_vclk_div_disable()
126 	return meson_parm_read(clk->map, &vclk->enable);  in meson_vclk_div_is_enabled()