Lines Matching +full:meson +full:- +full:gxbb +full:- +full:vpu
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include "gxbb.h"
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
230 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
231 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
543 * GXL and GXBB have different gp0_pll_dco (with
549 .index = -1,
616 * b) CCF has a clock hand-off mechanism to make the sure the
782 * GXL and GXBB have different SDM_EN registers. We
787 .index = -1,
995 * muxed by a glitch-free switch. The CCF can manage this glitch-free
996 * mux because it does top-to-bottom updates the each clock tree and
1493 /* VPU Clock */
1605 .name = "vpu",
1790 * GXL and GXBB have different hdmi_plls (with
1796 .index = -1,
1807 * GXL and GXBB have different hdmi_plls (with
1812 { .name = "hdmi_pll", .index = -1 },
3551 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3552 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3560 .name = "gxbb-clkc",
3566 MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver");