Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
26 #include "meson-eeclk.h"
29 #include <dt-bindings/clock/g12a-clkc.h>
32 .data = &(struct meson_clk_pll_data){
35 .shift = 28,
40 .shift = 0,
45 .shift = 10,
50 .shift = 0,
55 .shift = 31,
60 .shift = 29,
75 .data = &(struct clk_regmap_div_data){
77 .shift = 16,
101 .data = &(struct meson_clk_pll_data){
104 .shift = 28,
109 .shift = 0,
114 .shift = 10,
119 .shift = 31,
124 .shift = 29,
142 .data = &(struct clk_regmap_div_data){
144 .shift = 16,
160 .data = &(struct meson_clk_pll_data){
163 .shift = 28,
168 .shift = 0,
173 .shift = 10,
178 .shift = 31,
183 .shift = 29,
201 .data = &(struct clk_regmap_div_data){
203 .shift = 16,
219 .data = &(struct clk_regmap_gate_data){
236 .data = &(struct clk_regmap_gate_data){
292 .data = &(struct clk_regmap_gate_data){
310 * b) CCF has a clock hand-off mechanism to make the sure the
329 .data = &(struct clk_regmap_gate_data){
346 * b) CCF has a clock hand-off mechanism to make the sure the
355 .data = &(struct clk_regmap_mux_data){
358 .shift = 0,
376 .data = &(struct clk_regmap_mux_data){
379 .shift = 16,
390 /* This sub-tree is used a parking clock */
397 .data = &(struct meson_clk_cpu_dyndiv_data){
400 .shift = 4,
405 .shift = 26,
422 .data = &(struct clk_regmap_mux_data){
425 .shift = 2,
442 .data = &(struct clk_regmap_div_data){
444 .shift = 20,
459 .data = &(struct clk_regmap_mux_data){
462 .shift = 18,
472 /* This sub-tree is used a parking clock */
479 .data = &(struct clk_regmap_mux_data){
482 .shift = 10,
499 .data = &(struct clk_regmap_mux_data){
502 .shift = 11,
519 .data = &(struct clk_regmap_mux_data){
522 .shift = 11,
539 .data = &(struct clk_regmap_mux_data){
542 .shift = 0,
560 .data = &(struct meson_clk_cpu_dyndiv_data){
563 .shift = 4,
568 .shift = 26,
585 .data = &(struct clk_regmap_mux_data){
588 .shift = 2,
605 .data = &(struct clk_regmap_mux_data){
608 .shift = 16,
619 /* This sub-tree is used a parking clock */
626 .data = &(struct clk_regmap_div_data){
628 .shift = 20,
643 .data = &(struct clk_regmap_mux_data){
646 .shift = 18,
656 /* This sub-tree is used a parking clock */
663 .data = &(struct clk_regmap_mux_data){
666 .shift = 10,
683 .data = &(struct clk_regmap_mux_data){
686 .shift = 11,
705 .data = &(struct clk_regmap_mux_data){
708 .shift = 0,
725 .data = &(struct clk_regmap_mux_data){
728 .shift = 16,
745 .data = &(struct clk_regmap_div_data){
747 .shift = 4,
762 .data = &(struct clk_regmap_mux_data){
765 .shift = 2,
780 .data = &(struct clk_regmap_div_data){
782 .shift = 20,
797 .data = &(struct clk_regmap_mux_data){
800 .shift = 18,
815 .data = &(struct clk_regmap_mux_data){
818 .shift = 10,
833 .data = &(struct clk_regmap_mux_data){
836 .shift = 11,
851 .data = &(struct clk_regmap_mux_data){
854 .shift = 24,
869 .data = &(struct clk_regmap_mux_data){
872 .shift = 25,
887 .data = &(struct clk_regmap_mux_data){
890 .shift = 26,
905 .data = &(struct clk_regmap_mux_data){
908 .shift = 27,
922 unsigned long event, void *data) in g12a_cpu_clk_mux_notifier_cb() argument
947 unsigned long event, void *data) in g12a_cpu_clk_postmux_notifier_cb() argument
958 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
959 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
960 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
961 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
962 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
964 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
965 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
969 clk_hw_set_parent(nb_data->cpu_clk_premux1, in g12a_cpu_clk_postmux_notifier_cb()
970 nb_data->xtal); in g12a_cpu_clk_postmux_notifier_cb()
973 clk_hw_set_parent(nb_data->cpu_clk_postmux1, in g12a_cpu_clk_postmux_notifier_cb()
974 nb_data->cpu_clk_premux1); in g12a_cpu_clk_postmux_notifier_cb()
977 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
978 nb_data->cpu_clk_postmux1); in g12a_cpu_clk_postmux_notifier_cb()
983 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
984 * \- cpu_clk_postmux1 in g12a_cpu_clk_postmux_notifier_cb()
985 * \- cpu_clk_premux1 in g12a_cpu_clk_postmux_notifier_cb()
986 * \- xtal in g12a_cpu_clk_postmux_notifier_cb()
1001 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
1002 nb_data->cpu_clk_postmux0); in g12a_cpu_clk_postmux_notifier_cb()
1007 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
1008 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
1009 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
1010 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1011 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1013 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1014 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1050 unsigned long event, void *data) in g12a_sys_pll_notifier_cb() argument
1061 * \- sys_pll in g12a_sys_pll_notifier_cb()
1062 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1066 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1067 nb_data->cpu_clk_dyn); in g12a_sys_pll_notifier_cb()
1072 * \- cpu_clk_dyn in g12a_sys_pll_notifier_cb()
1073 * \- cpu_clk_dynX in g12a_sys_pll_notifier_cb()
1074 * \- cpu_clk_dynX_sel in g12a_sys_pll_notifier_cb()
1075 * \- cpu_clk_dynX_div in g12a_sys_pll_notifier_cb()
1076 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1077 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1091 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1092 nb_data->sys_pll); in g12a_sys_pll_notifier_cb()
1098 * \- sys_pll in g12a_sys_pll_notifier_cb()
1099 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1133 .data = &(struct clk_regmap_gate_data){
1151 .index = -1,
1162 .data = &(struct clk_regmap_gate_data){
1207 .data = &(struct clk_regmap_div_data){
1209 .shift = 3,
1218 .index = -1,
1225 .data = &(struct clk_regmap_gate_data){
1244 .data = &(struct clk_regmap_div_data){
1246 .shift = 6,
1255 .index = -1,
1262 .data = &(struct clk_regmap_gate_data){
1281 .data = &(struct clk_regmap_div_data){
1283 .shift = 9,
1292 .index = -1,
1299 .data = &(struct clk_regmap_gate_data){
1318 .data = &(struct clk_regmap_div_data){
1320 .shift = 20,
1329 .index = -1,
1336 .data = &(struct clk_regmap_gate_data){
1447 .data = &(struct clk_regmap_mux_data){
1450 .shift = 3,
1470 .data = &(struct clk_regmap_gate_data){
1490 .data = &(struct clk_regmap_mux_data){
1493 .shift = 6,
1513 .data = &(struct clk_regmap_gate_data){
1533 .data = &(struct clk_regmap_mux_data){
1536 .shift = 9,
1556 .data = &(struct clk_regmap_gate_data){
1576 .data = &(struct clk_regmap_mux_data){
1579 .shift = 20,
1599 .data = &(struct clk_regmap_gate_data){
1636 .data = &(struct meson_clk_pll_data){
1639 .shift = 28,
1644 .shift = 0,
1649 .shift = 10,
1654 .shift = 0,
1659 .shift = 31,
1664 .shift = 29,
1682 .data = &(struct clk_regmap_div_data){
1684 .shift = 16,
1701 .data = &(struct meson_clk_pll_data){
1704 .shift = 28,
1709 .shift = 0,
1714 .shift = 10,
1719 .shift = 0,
1724 .shift = 31,
1729 .shift = 29,
1746 .data = &(struct clk_regmap_div_data){
1748 .shift = 16,
1776 .data = &(struct meson_clk_pll_data){
1779 .shift = 28,
1784 .shift = 0,
1789 .shift = 10,
1794 .shift = 0,
1799 .shift = 31,
1804 .shift = 29,
1823 .data = &(struct clk_regmap_div_data){
1825 .shift = 16,
1868 .data = &(struct meson_clk_pll_data){
1871 .shift = 28,
1876 .shift = 0,
1881 .shift = 10,
1886 .shift = 0,
1891 .shift = 31,
1896 .shift = 29,
1928 .data = &(struct clk_regmap_div_data){
1930 .shift = 16,
1962 .data = &(struct meson_clk_pll_data){
1965 .shift = 28,
1970 .shift = 0,
1975 .shift = 10,
1980 .shift = 0,
1985 .shift = 30,
1990 .shift = 29,
2010 .data = &(struct clk_regmap_div_data){
2012 .shift = 16,
2028 .data = &(struct clk_regmap_div_data){
2030 .shift = 18,
2046 .data = &(struct clk_regmap_div_data){
2048 .shift = 20,
2075 .data = &(struct clk_regmap_gate_data){
2101 .data = &(struct clk_regmap_gate_data){
2127 .data = &(struct clk_regmap_gate_data){
2155 .data = &(struct clk_regmap_gate_data){
2183 .data = &(struct clk_regmap_mux_data){
2186 .shift = 5,
2217 .data = &(struct meson_clk_mpll_data){
2220 .shift = 0,
2225 .shift = 30,
2230 .shift = 20,
2235 .shift = 29,
2252 .data = &(struct clk_regmap_gate_data){
2270 .data = &(struct meson_clk_mpll_data){
2273 .shift = 0,
2278 .shift = 30,
2283 .shift = 20,
2288 .shift = 29,
2305 .data = &(struct clk_regmap_gate_data){
2323 .data = &(struct meson_clk_mpll_data){
2326 .shift = 0,
2331 .shift = 30,
2336 .shift = 20,
2341 .shift = 29,
2358 .data = &(struct clk_regmap_gate_data){
2376 .data = &(struct meson_clk_mpll_data){
2379 .shift = 0,
2384 .shift = 30,
2389 .shift = 20,
2394 .shift = 29,
2411 .data = &(struct clk_regmap_gate_data){
2436 .data = &(struct clk_regmap_mux_data){
2439 .shift = 12,
2451 .data = &(struct clk_regmap_div_data){
2453 .shift = 0,
2468 .data = &(struct clk_regmap_gate_data){
2499 .data = &(struct clk_regmap_mux_data){
2502 .shift = 9,
2514 .data = &(struct clk_regmap_div_data){
2516 .shift = 0,
2531 .data = &(struct clk_regmap_gate_data){
2548 .data = &(struct clk_regmap_mux_data){
2551 .shift = 25,
2563 .data = &(struct clk_regmap_div_data){
2565 .shift = 16,
2580 .data = &(struct clk_regmap_gate_data){
2597 .data = &(struct clk_regmap_mux_data){
2600 .shift = 9,
2612 .data = &(struct clk_regmap_div_data){
2614 .shift = 0,
2629 .data = &(struct clk_regmap_gate_data){
2647 .data = &(struct meson_vid_pll_div_data){
2650 .shift = 0,
2655 .shift = 16,
2674 .data = &(struct clk_regmap_mux_data){
2677 .shift = 18,
2693 .data = &(struct clk_regmap_gate_data){
2722 .data = &(struct clk_regmap_mux_data){
2725 .shift = 9,
2737 .data = &(struct clk_regmap_div_data){
2739 .shift = 0,
2752 .data = &(struct clk_regmap_gate_data){
2766 .data = &(struct clk_regmap_mux_data){
2769 .shift = 25,
2781 .data = &(struct clk_regmap_div_data){
2783 .shift = 16,
2796 .data = &(struct clk_regmap_gate_data){
2810 .data = &(struct clk_regmap_mux_data){
2813 .shift = 31,
2844 .data = &(struct clk_regmap_mux_data){
2847 .shift = 9,
2860 .data = &(struct clk_regmap_div_data){
2862 .shift = 0,
2878 .data = &(struct clk_regmap_gate_data){
2894 .data = &(struct clk_regmap_mux_data){
2897 .shift = 9,
2910 .data = &(struct clk_regmap_div_data){
2912 .shift = 0,
2928 .data = &(struct clk_regmap_gate_data){
2944 .data = &(struct clk_regmap_mux_data){
2947 .shift = 25,
2960 .data = &(struct clk_regmap_div_data){
2962 .shift = 16,
2978 .data = &(struct clk_regmap_gate_data){
3007 .data = &(struct clk_regmap_mux_data){
3010 .shift = 9,
3022 .data = &(struct clk_regmap_div_data){
3024 .shift = 0,
3039 .data = &(struct clk_regmap_gate_data){
3055 .data = &(struct clk_regmap_mux_data){
3058 .shift = 25,
3070 .data = &(struct clk_regmap_div_data){
3072 .shift = 16,
3087 .data = &(struct clk_regmap_gate_data){
3103 .data = &(struct clk_regmap_mux_data){
3106 .shift = 31,
3125 .data = &(struct clk_regmap_gate_data){
3150 .data = &(struct clk_regmap_mux_data){
3153 .shift = 16,
3165 .data = &(struct clk_regmap_mux_data){
3168 .shift = 16,
3180 .data = &(struct clk_regmap_gate_data){
3194 .data = &(struct clk_regmap_gate_data){
3207 .data = &(struct clk_regmap_div_data){
3209 .shift = 0,
3224 .data = &(struct meson_vclk_div_data){
3227 .shift = 0,
3232 .shift = 16,
3237 .shift = 17,
3254 .data = &(struct clk_regmap_gate_data){
3268 .data = &(struct meson_vclk_gate_data){
3271 .shift = 19,
3276 .shift = 15,
3290 .data = &(struct clk_regmap_gate_data){
3304 .data = &(struct clk_regmap_gate_data){
3318 .data = &(struct clk_regmap_gate_data){
3332 .data = &(struct clk_regmap_gate_data){
3346 .data = &(struct clk_regmap_gate_data){
3360 .data = &(struct clk_regmap_gate_data){
3374 .data = &(struct clk_regmap_gate_data){
3388 .data = &(struct clk_regmap_gate_data){
3402 .data = &(struct clk_regmap_gate_data){
3416 .data = &(struct clk_regmap_gate_data){
3552 .data = &(struct clk_regmap_mux_data){
3555 .shift = 28,
3568 .data = &(struct clk_regmap_mux_data){
3571 .shift = 20,
3584 .data = &(struct clk_regmap_mux_data){
3587 .shift = 12,
3600 .data = &(struct clk_regmap_mux_data){
3603 .shift = 28,
3631 .data = &(struct clk_regmap_mux_data){
3634 .shift = 16,
3647 .data = &(struct clk_regmap_gate_data){
3663 .data = &(struct clk_regmap_gate_data){
3679 .data = &(struct clk_regmap_gate_data){
3695 .data = &(struct clk_regmap_gate_data){
3711 .data = &(struct clk_regmap_gate_data){
3740 .data = &(struct clk_regmap_mux_data){
3743 .shift = 12,
3766 .data = &(struct clk_regmap_div_data){
3768 .shift = 0,
3784 .data = &(struct clk_regmap_gate_data){
3813 .data = &(struct clk_regmap_mux_data){
3816 .shift = 9,
3827 .data = &(struct clk_regmap_div_data){
3829 .shift = 0,
3844 .data = &(struct clk_regmap_gate_data){
3869 .data = &(struct clk_regmap_mux_data){
3872 .shift = 9,
3885 .data = &(struct clk_regmap_div_data){
3887 .shift = 0,
3900 .data = &(struct clk_regmap_gate_data){
3915 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3916 * mux because it does top-to-bottom updates the each clock tree and
3931 .data = &(struct clk_regmap_mux_data){
3934 .shift = 9,
3952 .data = &(struct clk_regmap_div_data){
3954 .shift = 0,
3969 .data = &(struct clk_regmap_gate_data){
3985 .data = &(struct clk_regmap_mux_data){
3988 .shift = 25,
4006 .data = &(struct clk_regmap_div_data){
4008 .shift = 16,
4023 .data = &(struct clk_regmap_gate_data){
4044 .data = &(struct clk_regmap_mux_data){
4047 .shift = 31,
4059 .data = &(struct clk_regmap_div_data){
4061 .shift = 0,
4075 .data = &(struct clk_regmap_gate_data){
4101 .data = &(struct clk_regmap_mux_data){
4104 .shift = 7,
4115 .data = &(struct clk_regmap_div_data){
4117 .shift = 0,
4132 .data = &(struct clk_regmap_gate_data){
4148 .data = &(struct clk_regmap_mux_data){
4151 .shift = 23,
4162 .data = &(struct clk_regmap_div_data){
4164 .shift = 16,
4179 .data = &(struct clk_regmap_gate_data){
4208 .data = &(struct clk_regmap_mux_data){
4211 .shift = 9,
4222 .data = &(struct clk_regmap_div_data){
4224 .shift = 0,
4239 .data = &(struct clk_regmap_gate_data){
4255 .data = &(struct clk_regmap_mux_data){
4258 .shift = 25,
4269 .data = &(struct clk_regmap_div_data){
4271 .shift = 16,
4286 .data = &(struct clk_regmap_gate_data){
5425 struct device *dev = &pdev->dev; in meson_g12b_dvfs_setup()
5502 struct device *dev = &pdev->dev; in meson_g12a_dvfs_setup()
5542 eeclkc_data = of_device_get_match_data(&pdev->dev); in meson_g12a_probe()
5544 return -EINVAL; in meson_g12a_probe()
5553 if (g12a_data->dvfs_setup) in meson_g12a_probe()
5554 return g12a_data->dvfs_setup(pdev); in meson_g12a_probe()
5599 .compatible = "amlogic,g12a-clkc",
5600 .data = &g12a_clkc_data.eeclkc_data
5603 .compatible = "amlogic,g12b-clkc",
5604 .data = &g12b_clkc_data.eeclkc_data
5607 .compatible = "amlogic,sm1-clkc",
5608 .data = &sm1_clkc_data.eeclkc_data
5617 .name = "g12a-clkc",