Lines Matching +full:mux +full:- +full:ssi0
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled()
93 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
94 -1, -1, -1, -1, -1, -1, -1, 0x4,
95 -1, -1, -1, -1, -1, -1, -1, -1,
96 -1, -1, -1, -1, -1, -1, -1, 0x5,
97 -1, -1, -1, -1, -1, -1, -1, -1,
98 -1, -1, -1, -1, -1, -1, -1, -1,
99 -1, -1, -1, -1, -1, -1, -1, -1,
100 -1, -1, -1, -1, -1, -1, -1, 0x6,
114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
204 /* Custom (SoC-specific) OTG PHY */
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
217 .mux = { CGU_REG_CPCCR, 30, 2 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
223 .mux = { CGU_REG_CPCCR, 28, 2 },
229 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
230 .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
241 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
242 .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
247 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
248 .mux = { CGU_REG_CPCCR, 26, 2 },
249 .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
254 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
255 .mux = { CGU_REG_CPCCR, 24, 2 },
260 .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
261 .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
266 .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
267 .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
278 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
279 .mux = { CGU_REG_DDRCDR, 30, 2 },
288 .mux = { CGU_REG_MACCDR, 30, 2 },
297 .mux = { CGU_REG_LPCDR, 30, 2 },
306 .mux = { CGU_REG_MSC0CDR, 30, 2 },
311 .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
318 .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
327 .mux = { CGU_REG_SSICDR, 30, 2 },
339 .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 },
340 .mux = { CGU_REG_SSICDR, 29, 1 },
352 .mux = { CGU_REG_OPCR, 2, 1},
356 /* Gate-only clocks */
360 .parents = { X1830_CLK_AHB2, -1, -1, -1 },
366 .parents = { X1830_CLK_AHB2, -1, -1, -1 },
372 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
377 "ssi0", CGU_CLK_GATE,
378 .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
384 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
390 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
396 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
402 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
408 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
414 .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
420 .parents = { X1830_CLK_SSIPLL, -1, -1, -1 },
426 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
432 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
438 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
444 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
470 * in the case where the device node is compatible with "simple-mfd".
472 CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init);