Lines Matching +full:mux +full:- +full:ssi0
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
86 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
142 .bypass_bit = -1,
159 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
167 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
175 CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
184 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
192 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
201 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
211 .mux = { CGU_REG_MSC0CDR, 30, 1 },
212 .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 },
218 .mux = { CGU_REG_MSC1CDR, 30, 1 },
219 .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 },
225 .mux = { CGU_REG_MSC2CDR, 30, 1 },
226 .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 },
232 .mux = { CGU_REG_CIMCDR, 31, 1 },
233 .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
239 .mux = { CGU_REG_UHCCDR, 29, 1 },
240 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
245 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 },
246 .mux = { CGU_REG_GPUCDR, 31, 1 },
247 .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
253 .mux = { CGU_REG_BCHCDR, 31, 1 },
254 .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 },
260 .mux = { CGU_REG_LPCDR, 29, 1 },
261 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
267 .mux = { CGU_REG_GPSCDR, 31, 1 },
268 .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
276 .parents = { JZ4770_CLK_EXT, -1,
278 .mux = { CGU_REG_SSICDR, 30, 2 },
279 .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 },
283 .parents = { JZ4770_CLK_EXT, -1,
285 .mux = { CGU_REG_PCMCDR, 30, 2 },
286 .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 },
290 .parents = { JZ4770_CLK_EXT, -1,
292 .mux = { CGU_REG_I2SCDR, 30, 2 },
293 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
298 .parents = { JZ4770_CLK_EXT, -1,
300 .mux = { CGU_REG_USBCDR, 30, 2 },
301 .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
305 /* Gate-only clocks */
308 "ssi0", CGU_CLK_GATE,
427 .parents = { JZ4770_CLK_UHC, -1, -1, -1 },
440 .mux = { CGU_REG_OPCR, 2, 1},
463 CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);