Lines Matching full:parents
94 .parents = { JZ4760_CLK_EXT },
119 .parents = { JZ4760_CLK_EXT },
149 .parents = { JZ4760_CLK_PLL0, },
157 .parents = { JZ4760_CLK_PLL0, },
165 .parents = { JZ4760_CLK_PLL0, },
173 .parents = { JZ4760_CLK_PLL0, },
182 * Disabling MCLK or its parents will render DRAM
186 .parents = { JZ4760_CLK_PLL0, },
194 .parents = { JZ4760_CLK_PLL0, },
205 .parents = { JZ4760_CLK_PLL0 },
216 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
223 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
230 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
236 .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT, },
242 .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE, },
248 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
258 .parents = { JZ4760_CLK_EXT, -1,
266 .parents = { JZ4760_CLK_EXT, -1,
273 .parents = { JZ4760_CLK_EXT, -1,
283 .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
289 .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
297 .parents = { JZ4760_CLK_PLL0_HALF },
306 .parents = { JZ4760_CLK_SSI_MUX, },
311 .parents = { JZ4760_CLK_SSI_MUX, },
316 .parents = { JZ4760_CLK_SSI_MUX, },
321 .parents = { JZ4760_CLK_H2CLK, },
326 .parents = { JZ4760_CLK_HCLK, },
331 .parents = { JZ4760_CLK_HCLK, },
336 .parents = { JZ4760_CLK_EXT, },
341 .parents = { JZ4760_CLK_EXT, },
346 .parents = { JZ4760_CLK_EXT, },
351 .parents = { JZ4760_CLK_EXT, },
356 .parents = { JZ4760_CLK_EXT, },
361 .parents = { JZ4760_CLK_EXT, },
366 .parents = { JZ4760_CLK_HCLK, },
371 .parents = { JZ4760_CLK_EXT, },
376 .parents = { JZ4760_CLK_EXT, },
381 .parents = { JZ4760_CLK_HCLK, },
386 .parents = { JZ4760_CLK_MMC_MUX, },
391 .parents = { JZ4760_CLK_MMC_MUX, },
396 .parents = { JZ4760_CLK_MMC_MUX, },
401 .parents = { JZ4760_CLK_UHC, },
406 .parents = { JZ4760_CLK_OTG },
413 .parents = { JZ4760_CLK_EXT },
418 .parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K, },