1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2017-2018 NXP.
10 #include <linux/clk-provider.h>
94 		struct clk_pll14xx *pll, unsigned long rate)  in imx_get_pll_settings()  argument
96 	const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;  in imx_get_pll_settings()
99 	for (i = 0; i < pll->rate_count; i++)  in imx_get_pll_settings()
106 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv,  in pll14xx_calc_rate()  argument
125 	/* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */  in pll1443x_calc_kdiv()
126 	kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536);  in pll1443x_calc_kdiv()
131 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate,  in imx_pll14xx_calc_settings()  argument
140 	 * Fractional PLL constrains:  in imx_pll14xx_calc_settings()
145 	 * d) -32768 <= k <= 32767  in imx_pll14xx_calc_settings()
152 	tt = imx_get_pll_settings(pll, rate);  in imx_pll14xx_calc_settings()
154 		pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n",  in imx_pll14xx_calc_settings()
155 			 clk_hw_get_name(&pll->hw), prate, rate);  in imx_pll14xx_calc_settings()
156 		t->rate = tt->rate;  in imx_pll14xx_calc_settings()
157 		t->mdiv = tt->mdiv;  in imx_pll14xx_calc_settings()
158 		t->pdiv = tt->pdiv;  in imx_pll14xx_calc_settings()
159 		t->sdiv = tt->sdiv;  in imx_pll14xx_calc_settings()
160 		t->kdiv = tt->kdiv;  in imx_pll14xx_calc_settings()
164 	pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);  in imx_pll14xx_calc_settings()
168 	pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);  in imx_pll14xx_calc_settings()
171 	rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate);  in imx_pll14xx_calc_settings()
172 	rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate);  in imx_pll14xx_calc_settings()
176 		pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",  in imx_pll14xx_calc_settings()
177 			 clk_hw_get_name(&pll->hw), prate, rate,  in imx_pll14xx_calc_settings()
179 		fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);  in imx_pll14xx_calc_settings()
180 		t->rate = (unsigned int)fout;  in imx_pll14xx_calc_settings()
181 		t->mdiv = mdiv;  in imx_pll14xx_calc_settings()
182 		t->pdiv = pdiv;  in imx_pll14xx_calc_settings()
183 		t->sdiv = sdiv;  in imx_pll14xx_calc_settings()
184 		t->kdiv = kdiv;  in imx_pll14xx_calc_settings()
196 			fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);  in imx_pll14xx_calc_settings()
199 			dist = abs((long)rate - (long)fout);  in imx_pll14xx_calc_settings()
202 				t->rate = (unsigned int)fout;  in imx_pll14xx_calc_settings()
203 				t->mdiv = mdiv;  in imx_pll14xx_calc_settings()
204 				t->pdiv = pdiv;  in imx_pll14xx_calc_settings()
205 				t->sdiv = sdiv;  in imx_pll14xx_calc_settings()
206 				t->kdiv = kdiv;  in imx_pll14xx_calc_settings()
215 		 clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,  in imx_pll14xx_calc_settings()
216 		 t->mdiv, t->kdiv);  in imx_pll14xx_calc_settings()
222 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1416x_round_rate()  local
223 	const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;  in clk_pll1416x_round_rate()
227 	for (i = 0; i < pll->rate_count; i++)  in clk_pll1416x_round_rate()
232 	return rate_table[pll->rate_count - 1].rate;  in clk_pll1416x_round_rate()
238 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1443x_round_rate()  local
241 	imx_pll14xx_calc_settings(pll, rate, *prate, &t);  in clk_pll1443x_round_rate()
249 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_recalc_rate()  local
252 	pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);  in clk_pll14xx_recalc_rate()
257 	if (pll->type == PLL_1443X) {  in clk_pll14xx_recalc_rate()
258 		pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);  in clk_pll14xx_recalc_rate()
264 	return pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, parent_rate);  in clk_pll14xx_recalc_rate()
275 	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;  in clk_pll14xx_mp_change()
278 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)  in clk_pll14xx_wait_lock()  argument
282 	return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0,  in clk_pll14xx_wait_lock()
289 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1416x_set_rate()  local
294 	rate = imx_get_pll_settings(pll, drate);  in clk_pll1416x_set_rate()
296 		pr_err("Invalid rate %lu for pll clk %s\n", drate,  in clk_pll1416x_set_rate()
298 		return -EINVAL;  in clk_pll1416x_set_rate()
301 	tmp = readl_relaxed(pll->base + DIV_CTL0);  in clk_pll1416x_set_rate()
305 		tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv);  in clk_pll1416x_set_rate()
306 		writel_relaxed(tmp, pll->base + DIV_CTL0);  in clk_pll1416x_set_rate()
311 	/* Bypass clock and set lock to pll output lock */  in clk_pll1416x_set_rate()
312 	tmp = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
314 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
318 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
322 	writel(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
324 	div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) |  in clk_pll1416x_set_rate()
325 		FIELD_PREP(SDIV_MASK, rate->sdiv);  in clk_pll1416x_set_rate()
326 	writel_relaxed(div_val, pll->base + DIV_CTL0);  in clk_pll1416x_set_rate()
329 	 * According to SPEC, t3 - t2 need to be greater than  in clk_pll1416x_set_rate()
338 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
341 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll1416x_set_rate()
347 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
355 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1443x_set_rate()  local
360 	imx_pll14xx_calc_settings(pll, drate, prate, &rate);  in clk_pll1443x_set_rate()
362 	div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);  in clk_pll1443x_set_rate()
365 		/* only sdiv and/or kdiv changed - no need to RESET PLL */  in clk_pll1443x_set_rate()
368 		writel_relaxed(div_ctl0, pll->base + DIV_CTL0);  in clk_pll1443x_set_rate()
371 			       pll->base + DIV_CTL1);  in clk_pll1443x_set_rate()
377 	gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
379 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
383 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
388 	writel_relaxed(div_ctl0, pll->base + DIV_CTL0);  in clk_pll1443x_set_rate()
390 	writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1);  in clk_pll1443x_set_rate()
393 	 * According to SPEC, t3 - t2 need to be greater than  in clk_pll1443x_set_rate()
402 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
405 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll1443x_set_rate()
411 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
418 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_prepare()  local
423 	 * RESETB = 1 from 0, PLL starts its normal  in clk_pll14xx_prepare()
426 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
430 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
432 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
434 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll14xx_prepare()
439 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
446 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_is_prepared()  local
449 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_is_prepared()
456 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_unprepare()  local
463 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
465 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
494 	struct clk_pll14xx *pll;  in imx_dev_clk_hw_pll14xx()  local
500 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in imx_dev_clk_hw_pll14xx()
501 	if (!pll)  in imx_dev_clk_hw_pll14xx()
502 		return ERR_PTR(-ENOMEM);  in imx_dev_clk_hw_pll14xx()
505 	init.flags = pll_clk->flags;  in imx_dev_clk_hw_pll14xx()
509 	switch (pll_clk->type) {  in imx_dev_clk_hw_pll14xx()
511 		if (!pll_clk->rate_table)  in imx_dev_clk_hw_pll14xx()
520 		pr_err("Unknown pll type for pll clk %s\n", name);  in imx_dev_clk_hw_pll14xx()
521 		kfree(pll);  in imx_dev_clk_hw_pll14xx()
522 		return ERR_PTR(-EINVAL);  in imx_dev_clk_hw_pll14xx()
525 	pll->base = base;  in imx_dev_clk_hw_pll14xx()
526 	pll->hw.init = &init;  in imx_dev_clk_hw_pll14xx()
527 	pll->type = pll_clk->type;  in imx_dev_clk_hw_pll14xx()
528 	pll->rate_table = pll_clk->rate_table;  in imx_dev_clk_hw_pll14xx()
529 	pll->rate_count = pll_clk->rate_count;  in imx_dev_clk_hw_pll14xx()
531 	val = readl_relaxed(pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
533 	writel_relaxed(val, pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
535 	hw = &pll->hw;  in imx_dev_clk_hw_pll14xx()
539 		pr_err("failed to register pll %s %d\n", name, ret);  in imx_dev_clk_hw_pll14xx()
540 		kfree(pll);  in imx_dev_clk_hw_pll14xx()