Lines Matching +full:0 +full:- +full:datasheet

1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define CCM_MPCTL	0x00
21 #define CCM_UPCTL	0x04
22 #define CCM_CCTL	0x08
23 #define CCM_CGCR0	0x0C
24 #define CCM_CGCR1	0x10
25 #define CCM_CGCR2	0x14
26 #define CCM_PCDR0	0x18
27 #define CCM_PCDR1	0x1C
28 #define CCM_PCDR2	0x20
29 #define CCM_PCDR3	0x24
30 #define CCM_RCSR	0x28
31 #define CCM_CRDR	0x2C
32 #define CCM_DCVR0	0x30
33 #define CCM_DCVR1	0x34
34 #define CCM_DCVR2	0x38
35 #define CCM_DCVR3	0x3c
36 #define CCM_LTR0	0x40
37 #define CCM_LTR1	0x44
38 #define CCM_LTR2	0x48
39 #define CCM_LTR3	0x4c
40 #define CCM_MCR		0x64
81 	clk[dummy] = imx_clk_fixed("dummy", 0);  in __mx25_clocks_init()
90 …clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)…  in __mx25_clocks_init()
109 	clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);  in __mx25_clocks_init()
113 	clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);  in __mx25_clocks_init()
117 	clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);  in __mx25_clocks_init()
121 	clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);  in __mx25_clocks_init()
125 	clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);  in __mx25_clocks_init()
154 	/* CCM_CGCR0(29-31): reserved */  in __mx25_clocks_init()
155 	/* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */  in __mx25_clocks_init()
166 	/* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */  in __mx25_clocks_init()
170 	/* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */  in __mx25_clocks_init()
171 	/* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */  in __mx25_clocks_init()
172 	/* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */  in __mx25_clocks_init()
177 	/* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */  in __mx25_clocks_init()
178 	/* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */  in __mx25_clocks_init()
179 	/* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */  in __mx25_clocks_init()
181 	/* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */  in __mx25_clocks_init()
182 	/* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */  in __mx25_clocks_init()
185 	/* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */  in __mx25_clocks_init()
187 	clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2),  0);  in __mx25_clocks_init()
191 	/* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */  in __mx25_clocks_init()
206 	/* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */  in __mx25_clocks_init()
231 	ccm = of_iomap(np, 0);  in mx25_clocks_init_dt()
238 CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);