125 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)  in imx_get_pll_settings()  argument
127 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in imx_get_pll_settings()
130 	for (i = 0; i < pll->rate_count; i++)  in imx_get_pll_settings()
140 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_round_rate()  local
141 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in clk_fracn_gppll_round_rate()
145 	for (i = 0; i < pll->rate_count; i++)  in clk_fracn_gppll_round_rate()
150 	return rate_table[pll->rate_count - 1].rate;  in clk_fracn_gppll_round_rate()
155 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_recalc_rate()  local
156 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in clk_fracn_gppll_recalc_rate()
163 	pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_recalc_rate()
166 	pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);  in clk_fracn_gppll_recalc_rate()
169 	pll_div = readl_relaxed(pll->base + PLL_DIV);  in clk_fracn_gppll_recalc_rate()
177 	 * the frac part. So find the accurate pll rate from the table  in clk_fracn_gppll_recalc_rate()
181 	for (i = 0; i < pll->rate_count; i++) {  in clk_fracn_gppll_recalc_rate()
205 	if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {  in clk_fracn_gppll_recalc_rate()
218 static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)  in clk_fracn_gppll_wait_lock()  argument
222 	return readl_poll_timeout(pll->base + PLL_STATUS, val,  in clk_fracn_gppll_wait_lock()
229 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_set_rate()  local
234 	rate = imx_get_pll_settings(pll, drate);  in clk_fracn_gppll_set_rate()
236 	/* Hardware control select disable. PLL is control by register */  in clk_fracn_gppll_set_rate()
237 	tmp = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
239 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
242 	tmp = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
244 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
248 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
252 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
256 	writel_relaxed(pll_div, pll->base + PLL_DIV);  in clk_fracn_gppll_set_rate()
257 	readl(pll->base + PLL_DIV);  in clk_fracn_gppll_set_rate()
258 	if (pll->flags & CLK_FRACN_GPPLL_FRACN) {  in clk_fracn_gppll_set_rate()
259 		writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);  in clk_fracn_gppll_set_rate()
260 		writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_set_rate()
261 		readl(pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_set_rate()
264 	/* Wait for 5us according to fracn mode pll doc */  in clk_fracn_gppll_set_rate()
269 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
270 	readl(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
273 	ret = clk_fracn_gppll_wait_lock(pll);  in clk_fracn_gppll_set_rate()
279 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
281 	ana_mfn = readl_relaxed(pll->base + PLL_STATUS);  in clk_fracn_gppll_set_rate()
291 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_prepare()  local
295 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
299 	if (pll->flags & CLK_FRACN_GPPLL_FRACN)  in clk_fracn_gppll_prepare()
300 		writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),  in clk_fracn_gppll_prepare()
301 			       pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_prepare()
304 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
307 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
308 	readl(pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
310 	ret = clk_fracn_gppll_wait_lock(pll);  in clk_fracn_gppll_prepare()
315 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
318 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
325 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_is_prepared()  local
328 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_is_prepared()
335 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_unprepare()  local
338 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_unprepare()
340 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_unprepare()
357 	struct clk_fracn_gppll *pll;  in _imx_clk_fracn_gppll()  local
362 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in _imx_clk_fracn_gppll()
363 	if (!pll)  in _imx_clk_fracn_gppll()
372 	pll->base = base;  in _imx_clk_fracn_gppll()
373 	pll->hw.init = &init;  in _imx_clk_fracn_gppll()
374 	pll->rate_table = pll_clk->rate_table;  in _imx_clk_fracn_gppll()
375 	pll->rate_count = pll_clk->rate_count;  in _imx_clk_fracn_gppll()
376 	pll->flags = pll_flags;  in _imx_clk_fracn_gppll()
378 	hw = &pll->hw;  in _imx_clk_fracn_gppll()
382 		pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);  in _imx_clk_fracn_gppll()
383 		kfree(pll);  in _imx_clk_fracn_gppll()