1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/hix5hd2-clock.h>
174 	val = readl_relaxed(clk->ctrl_reg);  in clk_ether_prepare()
175 	val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask;  in clk_ether_prepare()
176 	writel_relaxed(val, clk->ctrl_reg);  in clk_ether_prepare()
177 	val &= ~(clk->ctrl_rst_mask);  in clk_ether_prepare()
178 	writel_relaxed(val, clk->ctrl_reg);  in clk_ether_prepare()
180 	val = readl_relaxed(clk->phy_reg);  in clk_ether_prepare()
181 	val |= clk->phy_clk_mask;  in clk_ether_prepare()
182 	val &= ~(clk->phy_rst_mask);  in clk_ether_prepare()
183 	writel_relaxed(val, clk->phy_reg);  in clk_ether_prepare()
186 	val &= ~(clk->phy_clk_mask);  in clk_ether_prepare()
187 	val |= clk->phy_rst_mask;  in clk_ether_prepare()
188 	writel_relaxed(val, clk->phy_reg);  in clk_ether_prepare()
191 	val |= clk->phy_clk_mask;  in clk_ether_prepare()
192 	val &= ~(clk->phy_rst_mask);  in clk_ether_prepare()
193 	writel_relaxed(val, clk->phy_reg);  in clk_ether_prepare()
203 	val = readl_relaxed(clk->ctrl_reg);  in clk_ether_unprepare()
204 	val &= ~(clk->ctrl_clk_mask);  in clk_ether_unprepare()
205 	writel_relaxed(val, clk->ctrl_reg);  in clk_ether_unprepare()
218 	val = readl_relaxed(clk->ctrl_reg);  in clk_complex_enable()
219 	val |= clk->ctrl_clk_mask;  in clk_complex_enable()
220 	val &= ~(clk->ctrl_rst_mask);  in clk_complex_enable()
221 	writel_relaxed(val, clk->ctrl_reg);  in clk_complex_enable()
223 	val = readl_relaxed(clk->phy_reg);  in clk_complex_enable()
224 	val |= clk->phy_clk_mask;  in clk_complex_enable()
225 	val &= ~(clk->phy_rst_mask);  in clk_complex_enable()
226 	writel_relaxed(val, clk->phy_reg);  in clk_complex_enable()
236 	val = readl_relaxed(clk->ctrl_reg);  in clk_complex_disable()
237 	val |= clk->ctrl_rst_mask;  in clk_complex_disable()
238 	val &= ~(clk->ctrl_clk_mask);  in clk_complex_disable()
239 	writel_relaxed(val, clk->ctrl_reg);  in clk_complex_disable()
241 	val = readl_relaxed(clk->phy_reg);  in clk_complex_disable()
242 	val |= clk->phy_rst_mask;  in clk_complex_disable()
243 	val &= ~(clk->phy_clk_mask);  in clk_complex_disable()
244 	writel_relaxed(val, clk->phy_reg);  in clk_complex_disable()
256 	void __iomem *base = data->base;  in hix5hd2_clk_register_complex()
279 		p_clk->ctrl_reg = base + clks[i].ctrl_reg;  in hix5hd2_clk_register_complex()
280 		p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask;  in hix5hd2_clk_register_complex()
281 		p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask;  in hix5hd2_clk_register_complex()
282 		p_clk->phy_reg = base + clks[i].phy_reg;  in hix5hd2_clk_register_complex()
283 		p_clk->phy_clk_mask = clks[i].phy_clk_mask;  in hix5hd2_clk_register_complex()
284 		p_clk->phy_rst_mask = clks[i].phy_rst_mask;  in hix5hd2_clk_register_complex()
285 		p_clk->hw.init = &init;  in hix5hd2_clk_register_complex()
287 		clk = clk_register(NULL, &p_clk->hw);  in hix5hd2_clk_register_complex()
290 			pr_err("%s: failed to register clock %s\n",  in hix5hd2_clk_register_complex()
295 		data->clk_data.clks[clks[i].id] = clk;  in hix5hd2_clk_register_complex()
319 CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);