446 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_enable()  local
450 	if (pclk->lock)  in xgene_clk_enable()
451 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_enable()
453 	if (pclk->param.csr_reg) {  in xgene_clk_enable()
456 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
457 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
458 		data |= pclk->param.reg_clk_mask;  in xgene_clk_enable()
459 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
460 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
463 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,  in xgene_clk_enable()
467 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
468 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
469 		data &= ~pclk->param.reg_csr_mask;  in xgene_clk_enable()
470 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
471 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
474 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,  in xgene_clk_enable()
478 	if (pclk->lock)  in xgene_clk_enable()
479 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_enable()
486 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_disable()  local
490 	if (pclk->lock)  in xgene_clk_disable()
491 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_disable()
493 	if (pclk->param.csr_reg) {  in xgene_clk_disable()
496 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
497 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
498 		data |= pclk->param.reg_csr_mask;  in xgene_clk_disable()
499 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
500 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
503 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
504 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
505 		data &= ~pclk->param.reg_clk_mask;  in xgene_clk_disable()
506 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
507 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
510 	if (pclk->lock)  in xgene_clk_disable()
511 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_disable()
516 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_is_enabled()  local
519 	if (pclk->param.csr_reg) {  in xgene_clk_is_enabled()
521 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_is_enabled()
522 					pclk->param.reg_clk_offset);  in xgene_clk_is_enabled()
524 			str_enabled_disabled(data & pclk->param.reg_clk_mask));  in xgene_clk_is_enabled()
529 	return data & pclk->param.reg_clk_mask ? 1 : 0;  in xgene_clk_is_enabled()
535 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_recalc_rate()  local
538 	if (pclk->param.divider_reg) {  in xgene_clk_recalc_rate()
539 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_recalc_rate()
540 					pclk->param.reg_divider_offset);  in xgene_clk_recalc_rate()
541 		data >>= pclk->param.reg_divider_shift;  in xgene_clk_recalc_rate()
542 		data &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_recalc_rate()
559 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_set_rate()  local
565 	if (pclk->lock)  in xgene_clk_set_rate()
566 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_set_rate()
568 	if (pclk->param.divider_reg) {  in xgene_clk_set_rate()
573 		divider &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_set_rate()
574 		divider <<= pclk->param.reg_divider_shift;  in xgene_clk_set_rate()
577 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_set_rate()
578 				pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
579 		data &= ~(((1 << pclk->param.reg_divider_width) - 1)  in xgene_clk_set_rate()
580 				<< pclk->param.reg_divider_shift);  in xgene_clk_set_rate()
582 		xgene_clk_write(data, pclk->param.divider_reg +  in xgene_clk_set_rate()
583 					pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
590 	if (pclk->lock)  in xgene_clk_set_rate()
591 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_set_rate()
599 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_round_rate()  local
603 	if (pclk->param.divider_reg) {  in xgene_clk_round_rate()