30 #define PLATFORM_PLL	0  macro
260 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
273 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
286 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
299 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
339 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
413 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
426 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
434 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
450 		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
460 		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
479 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p2041_init_periph()
491 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
496 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
511 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5020_init_periph()
526 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
531 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
541 	cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;  in t1040_init_periph()
569 		.pll_mask = BIT(PLATFORM_PLL) |
587 		.pll_mask = BIT(PLATFORM_PLL) |
600 		.pll_mask = BIT(PLATFORM_PLL) |
615 		.pll_mask = BIT(PLATFORM_PLL) |
631 		.pll_mask = BIT(PLATFORM_PLL) |
647 		.pll_mask = BIT(PLATFORM_PLL) |
662 		.pll_mask = BIT(PLATFORM_PLL) |
674 		.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
684 		.pll_mask = BIT(PLATFORM_PLL) |
697 		.pll_mask = BIT(PLATFORM_PLL) |
712 		.pll_mask = BIT(PLATFORM_PLL) |
725 		.pll_mask = BIT(PLATFORM_PLL) |
738 		.pll_mask = BIT(PLATFORM_PLL) |
752 		.pll_mask = BIT(PLATFORM_PLL) |
765 		.pll_mask = BIT(PLATFORM_PLL) |
781 		.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
794 		.pll_mask = BIT(PLATFORM_PLL) |
811 		.pll_mask = BIT(PLATFORM_PLL) |
828 		.pll_mask = BIT(PLATFORM_PLL) |
1008 	plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);  in create_one_cmux()
1220 	if (cg->coreclk && idx != PLATFORM_PLL) {  in create_one_pll()
1229 		case PLATFORM_PLL:  in create_one_pll()
1249 		if (idx == PLATFORM_PLL)  in create_one_pll()
1265 	    ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))  in create_one_pll()
1278 		if (idx != PLATFORM_PLL && i >= 4)  in create_one_pll()
1361 	legacy_pll_init(np, PLATFORM_PLL);  in pltfrm_pll_init()
1422 		pll = &cg->pll[PLATFORM_PLL];  in clockgen_clk_get()