Lines Matching +full:div +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
34 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
40 struct clk *clk; member
45 struct clockgen_pll_div div[MAX_PLL_DIV]; member
54 int div; /* PLL_DIVn */ member
83 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
92 struct clk *sysclk, *coreclk;
94 struct clk *cmux[NUM_CMUX];
95 struct clk *hwaccel[NUM_HWACCEL];
96 struct clk *fman[2];
105 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
115 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
474 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
477 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
479 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
486 reg = ioread32be(&cg->guts->rcwsr[7]); in p4080_init_periph()
489 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
491 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
494 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
496 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
502 int div = PLL_DIV2; in p5020_init_periph() local
504 reg = ioread32be(&cg->guts->rcwsr[7]); in p5020_init_periph()
506 div = PLL_DIV4; in p5020_init_periph()
509 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
511 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
517 int div = PLL_DIV2; in p5040_init_periph() local
519 reg = ioread32be(&cg->guts->rcwsr[7]); in p5040_init_periph()
521 div = PLL_DIV4; in p5040_init_periph()
524 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
526 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
529 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
531 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
536 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
541 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
546 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
551 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
552 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
557 .compat = "fsl,b4420-clockgen",
558 .guts_compat = "fsl,b4860-device-config",
567 0, 1, 1, 1, -1
575 .compat = "fsl,b4860-clockgen",
576 .guts_compat = "fsl,b4860-device-config",
585 0, 1, 1, 1, -1
593 .compat = "fsl,ls1021a-clockgen",
598 0, -1
604 .compat = "fsl,ls1028a-clockgen",
613 0, 0, 0, 0, -1
620 .compat = "fsl,ls1043a-clockgen",
629 0, -1
636 .compat = "fsl,ls1046a-clockgen",
645 0, -1
652 .compat = "fsl,ls1088a-clockgen",
660 0, 0, -1
667 .compat = "fsl,ls1012a-clockgen",
672 0, -1
677 .compat = "fsl,ls2080a-clockgen",
682 0, 0, 1, 1, -1
690 .compat = "fsl,lx2160a-clockgen",
695 0, 0, 0, 0, 1, 1, 1, 1, -1
703 .compat = "fsl,p2041-clockgen",
704 .guts_compat = "fsl,qoriq-device-config-1.0",
710 0, 0, 1, 1, -1
716 .compat = "fsl,p3041-clockgen",
717 .guts_compat = "fsl,qoriq-device-config-1.0",
723 0, 0, 1, 1, -1
729 .compat = "fsl,p4080-clockgen",
730 .guts_compat = "fsl,qoriq-device-config-1.0",
736 0, 0, 0, 0, 1, 1, 1, 1, -1
743 .compat = "fsl,p5020-clockgen",
744 .guts_compat = "fsl,qoriq-device-config-1.0",
750 0, 1, -1
756 .compat = "fsl,p5040-clockgen",
757 .guts_compat = "fsl,p5040-device-config",
763 0, 0, 1, 1, -1
769 .compat = "fsl,t1023-clockgen",
770 .guts_compat = "fsl,t1023-device-config",
779 0, 0, -1
785 .compat = "fsl,t1040-clockgen",
786 .guts_compat = "fsl,t1040-device-config",
792 0, 0, 0, 0, -1
799 .compat = "fsl,t2080-clockgen",
800 .guts_compat = "fsl,t2080-device-config",
809 0, -1
816 .compat = "fsl,t4240-clockgen",
817 .guts_compat = "fsl,t4240-device-config",
826 0, 0, 1, -1
855 if (idx >= hwc->num_parents) in mux_set_parent()
856 return -EINVAL; in mux_set_parent()
858 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
859 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
870 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
872 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
874 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
899 int pll, div; in get_pll_div() local
901 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
904 pll = hwc->info->clksel[idx].pll; in get_pll_div()
905 div = hwc->info->clksel[idx].div; in get_pll_div()
907 return &cg->pll[pll].div[div]; in get_pll_div()
910 static struct clk * __init create_mux_common(struct clockgen *cg, in create_mux_common()
919 struct clk *clk; in create_mux_common() local
920 const struct clockgen_pll_div *div; in create_mux_common() local
930 hwc->clksel_to_parent[i] = -1; in create_mux_common()
932 div = get_pll_div(cg, hwc, i); in create_mux_common()
933 if (!div) in create_mux_common()
936 rate = clk_get_rate(div->clk); in create_mux_common()
938 if (hwc->info->clksel[i].flags & CLKSEL_80PCT && in create_mux_common()
946 parent_names[j] = div->name; in create_mux_common()
947 hwc->parent_to_clksel[j] = i; in create_mux_common()
948 hwc->clksel_to_parent[i] = j; in create_mux_common()
955 init.num_parents = hwc->num_parents = j; in create_mux_common()
957 hwc->hw.init = &init; in create_mux_common()
958 hwc->cg = cg; in create_mux_common()
960 clk = clk_register(NULL, &hwc->hw); in create_mux_common()
961 if (IS_ERR(clk)) { in create_mux_common()
963 PTR_ERR(clk)); in create_mux_common()
968 return clk; in create_mux_common()
971 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) in create_one_cmux()
974 const struct clockgen_pll_div *div; in create_one_cmux() local
983 if (cg->info.flags & CG_VER3) in create_one_cmux()
984 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; in create_one_cmux()
986 hwc->reg = cg->regs + 0x20 * idx; in create_one_cmux()
988 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; in create_one_cmux()
997 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in create_one_cmux()
998 div = get_pll_div(cg, hwc, clksel); in create_one_cmux()
999 if (!div) { in create_one_cmux()
1004 max_rate = clk_get_rate(div->clk); in create_one_cmux()
1008 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
1010 if (cg->info.flags & CG_CMUX_GE_PLAT) in create_one_cmux()
1016 pct80_rate, "cg-cmux%d", idx); in create_one_cmux()
1019 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) in create_one_hwaccel()
1027 hwc->reg = cg->regs + 0x20 * idx + 0x10; in create_one_hwaccel()
1028 hwc->info = cg->info.hwaccel[idx]; in create_one_hwaccel()
1031 "cg-hwaccel%d", idx); in create_one_hwaccel()
1038 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { in create_muxes()
1039 if (cg->info.cmux_to_group[i] < 0) in create_muxes()
1041 if (cg->info.cmux_to_group[i] >= in create_muxes()
1042 ARRAY_SIZE(cg->info.cmux_groups)) { in create_muxes()
1047 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
1050 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { in create_muxes()
1051 if (!cg->info.hwaccel[i]) in create_muxes()
1054 cg->hwaccel[i] = create_one_hwaccel(cg, i); in create_muxes()
1063 * contain a "clocks" property -- otherwise the input clocks may
1077 struct clk *clk; in core_mux_init() local
1087 clk = clockgen.cmux[idx]; in core_mux_init()
1089 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); in core_mux_init()
1091 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in core_mux_init()
1097 static struct clk __init
1102 if (of_property_read_u32(node, "clock-frequency", &rate)) in sysclk_from_fixed()
1103 return ERR_PTR(-ENODEV); in sysclk_from_fixed()
1108 static struct clk __init *input_clock(const char *name, struct clk *clk) in input_clock() argument
1113 input_name = __clk_get_name(clk); in input_clock()
1114 clk = clk_register_fixed_factor(NULL, name, input_name, in input_clock()
1116 if (IS_ERR(clk)) in input_clock()
1118 PTR_ERR(clk)); in input_clock()
1120 return clk; in input_clock()
1123 static struct clk __init *input_clock_by_name(const char *name, in input_clock_by_name()
1126 struct clk *clk; in input_clock_by_name() local
1128 clk = of_clk_get_by_name(clockgen.node, dtname); in input_clock_by_name()
1129 if (IS_ERR(clk)) in input_clock_by_name()
1130 return clk; in input_clock_by_name()
1132 return input_clock(name, clk); in input_clock_by_name()
1135 static struct clk __init *input_clock_by_index(const char *name, int idx) in input_clock_by_index()
1137 struct clk *clk; in input_clock_by_index() local
1139 clk = of_clk_get(clockgen.node, 0); in input_clock_by_index()
1140 if (IS_ERR(clk)) in input_clock_by_index()
1141 return clk; in input_clock_by_index()
1143 return input_clock(name, clk); in input_clock_by_index()
1146 static struct clk * __init create_sysclk(const char *name) in create_sysclk()
1149 struct clk *clk; in create_sysclk() local
1151 clk = sysclk_from_fixed(clockgen.node, name); in create_sysclk()
1152 if (!IS_ERR(clk)) in create_sysclk()
1153 return clk; in create_sysclk()
1155 clk = input_clock_by_name(name, "sysclk"); in create_sysclk()
1156 if (!IS_ERR(clk)) in create_sysclk()
1157 return clk; in create_sysclk()
1159 clk = input_clock_by_index(name, 0); in create_sysclk()
1160 if (!IS_ERR(clk)) in create_sysclk()
1161 return clk; in create_sysclk()
1165 clk = sysclk_from_fixed(sysclk, name); in create_sysclk()
1167 if (!IS_ERR(clk)) in create_sysclk()
1168 return clk; in create_sysclk()
1175 static struct clk * __init create_coreclk(const char *name) in create_coreclk()
1177 struct clk *clk; in create_coreclk() local
1179 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1180 if (!IS_ERR(clk)) in create_coreclk()
1181 return clk; in create_coreclk()
1189 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER)) in create_coreclk()
1190 return clk; in create_coreclk()
1198 struct clk *clk; in sysclk_init() local
1202 clk = clockgen.sysclk; in sysclk_init()
1203 if (clk) in sysclk_init()
1204 of_clk_add_provider(node, of_clk_src_simple_get, clk); in sysclk_init()
1213 struct clockgen_pll *pll = &cg->pll[idx]; in create_one_pll()
1214 const char *input = "cg-sysclk"; in create_one_pll()
1217 if (!(cg->info.pll_mask & (1 << idx))) in create_one_pll()
1220 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1221 if (IS_ERR(cg->coreclk)) in create_one_pll()
1224 input = "cg-coreclk"; in create_one_pll()
1227 if (cg->info.flags & CG_VER3) { in create_one_pll()
1230 reg = cg->regs + 0x60080; in create_one_pll()
1233 reg = cg->regs + 0x80; in create_one_pll()
1236 reg = cg->regs + 0xa0; in create_one_pll()
1239 reg = cg->regs + 0x10080; in create_one_pll()
1242 reg = cg->regs + 0x100a0; in create_one_pll()
1250 reg = cg->regs + 0xc00; in create_one_pll()
1252 reg = cg->regs + 0x800 + 0x20 * (idx - 1); in create_one_pll()
1264 if ((cg->info.flags & CG_VER3) || in create_one_pll()
1265 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1270 for (i = 0; i < ARRAY_SIZE(pll->div); i++) { in create_one_pll()
1271 struct clk *clk; in create_one_pll() local
1281 snprintf(pll->div[i].name, sizeof(pll->div[i].name), in create_one_pll()
1282 "cg-pll%d-div%d", idx, i + 1); in create_one_pll()
1284 clk = clk_register_fixed_factor(NULL, in create_one_pll()
1285 pll->div[i].name, input, 0, mult, i + 1); in create_one_pll()
1286 if (IS_ERR(clk)) { in create_one_pll()
1288 __func__, pll->div[i].name, PTR_ERR(clk)); in create_one_pll()
1292 pll->div[i].clk = clk; in create_one_pll()
1293 ret = clk_register_clkdev(clk, pll->div[i].name, NULL); in create_one_pll()
1296 __func__, pll->div[i].name, ret); in create_one_pll()
1305 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) in create_plls()
1313 struct clk **subclks; in legacy_pll_init()
1319 count = of_property_count_strings(np, "clock-output-names"); in legacy_pll_init()
1321 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); in legacy_pll_init()
1322 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); in legacy_pll_init()
1331 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1332 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1333 subclks[2] = pll->div[3].clk; in legacy_pll_init()
1335 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1336 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1337 subclks[2] = pll->div[2].clk; in legacy_pll_init()
1338 subclks[3] = pll->div[3].clk; in legacy_pll_init()
1341 onecell_data->clks = subclks; in legacy_pll_init()
1342 onecell_data->clk_num = count; in legacy_pll_init()
1346 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in legacy_pll_init()
1385 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) in clockgen_clk_get()
1388 struct clk *clk; in clockgen_clk_get() local
1392 if (clkspec->args_count < 2) { in clockgen_clk_get()
1394 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1397 type = clkspec->args[0]; in clockgen_clk_get()
1398 idx = clkspec->args[1]; in clockgen_clk_get()
1404 clk = cg->sysclk; in clockgen_clk_get()
1407 if (idx >= ARRAY_SIZE(cg->cmux)) in clockgen_clk_get()
1409 clk = cg->cmux[idx]; in clockgen_clk_get()
1412 if (idx >= ARRAY_SIZE(cg->hwaccel)) in clockgen_clk_get()
1414 clk = cg->hwaccel[idx]; in clockgen_clk_get()
1417 if (idx >= ARRAY_SIZE(cg->fman)) in clockgen_clk_get()
1419 clk = cg->fman[idx]; in clockgen_clk_get()
1422 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()
1423 if (idx >= ARRAY_SIZE(pll->div)) in clockgen_clk_get()
1425 clk = pll->div[idx].clk; in clockgen_clk_get()
1430 clk = cg->coreclk; in clockgen_clk_get()
1431 if (IS_ERR(clk)) in clockgen_clk_get()
1432 clk = NULL; in clockgen_clk_get()
1438 if (!clk) in clockgen_clk_get()
1439 return ERR_PTR(-ENOENT); in clockgen_clk_get()
1440 return clk; in clockgen_clk_get()
1444 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1515 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) in _clockgen_init()
1544 clockgen.sysclk = create_sysclk("cg-sysclk"); in _clockgen_init()
1545 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
1554 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in _clockgen_init()
1577 pdev = platform_device_register_simple("qoriq-cpufreq", -1, in clockgen_cpufreq_init()
1580 pr_err("Couldn't register qoriq-cpufreq err=%ld\n", in clockgen_cpufreq_init()
1587 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1588 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1589 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1590 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1591 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1592 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1593 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1594 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1595 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1596 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1597 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1598 CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
1599 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1600 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1601 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1602 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1603 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1604 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1605 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1606 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1607 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1610 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1611 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1612 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1613 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1614 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1615 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1616 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1617 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);