1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Microchip LAN966x SoC Clock driver.
11 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/microchip,lan966x.h>
87 	.name = "lan966x",
107 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_enable()  local
108 	u32 val = readl(gck->reg);  in lan966x_gck_enable()
111 	writel(val, gck->reg);  in lan966x_gck_enable()
118 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_disable()  local
119 	u32 val = readl(gck->reg);  in lan966x_gck_disable()
122 	writel(val, gck->reg);  in lan966x_gck_disable()
129 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_set_rate()  local
130 	u32 div, val = readl(gck->reg);  in lan966x_gck_set_rate()
133 		return -EINVAL;  in lan966x_gck_set_rate()
138 	val |= FIELD_PREP(GCK_PRESCALER, (div - 1));  in lan966x_gck_set_rate()
139 	writel(val, gck->reg);  in lan966x_gck_set_rate()
147 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_recalc_rate()  local
148 	u32 div, val = readl(gck->reg);  in lan966x_gck_recalc_rate()
166 		/* Allowed prescaler divider range is 0-255 */  in lan966x_gck_determine_rate()
167 		if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) {  in lan966x_gck_determine_rate()
168 			req->best_parent_hw = parent;  in lan966x_gck_determine_rate()
169 			req->best_parent_rate = clk_hw_get_rate(parent);  in lan966x_gck_determine_rate()
175 	return -EINVAL;  in lan966x_gck_determine_rate()
180 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_get_parent()  local
181 	u32 val = readl(gck->reg);  in lan966x_gck_get_parent()
188 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_set_parent()  local
189 	u32 val = readl(gck->reg);  in lan966x_gck_set_parent()
193 	writel(val, gck->reg);  in lan966x_gck_set_parent()
215 		return ERR_PTR(-ENOMEM);  in lan966x_gck_clk_register()
217 	priv->reg = base + (i * 4);  in lan966x_gck_clk_register()
218 	priv->hw.init = &init;  in lan966x_gck_clk_register()
219 	ret = devm_clk_hw_register(dev, &priv->hw);  in lan966x_gck_clk_register()
223 	return &priv->hw;  in lan966x_gck_clk_register()
231 	for (int i = data->num_generic_clks; i < data->num_total_clks; ++i) {  in lan966x_gate_clk_register()
232 		int idx = i - data->num_generic_clks;  in lan966x_gate_clk_register()
235 		desc = &data->clk_gate_desc[idx];  in lan966x_gate_clk_register()
237 		hw_data->hws[i] =  in lan966x_gate_clk_register()
238 			devm_clk_hw_register_gate(dev, desc->name,  in lan966x_gate_clk_register()
239 						  data->name, 0, gate_base,  in lan966x_gate_clk_register()
240 						  desc->bit_idx,  in lan966x_gate_clk_register()
243 		if (IS_ERR(hw_data->hws[i]))  in lan966x_gate_clk_register()
244 			return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),  in lan966x_gate_clk_register()
246 					     desc->name);  in lan966x_gate_clk_register()
256 	struct device *dev = &pdev->dev;  in lan966x_clk_probe()
263 		return -EINVAL;  in lan966x_clk_probe()
265 	hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, data->num_total_clks),  in lan966x_clk_probe()
268 		return -ENOMEM;  in lan966x_clk_probe()
276 	hw_data->num = data->num_generic_clks;  in lan966x_clk_probe()
278 	for (i = 0; i < data->num_generic_clks; i++) {  in lan966x_clk_probe()
279 		init.name = data->clk_name[i];  in lan966x_clk_probe()
280 		hw_data->hws[i] = lan966x_gck_clk_register(dev, i);  in lan966x_clk_probe()
281 		if (IS_ERR(hw_data->hws[i])) {  in lan966x_clk_probe()
284 			return PTR_ERR(hw_data->hws[i]);  in lan966x_clk_probe()
290 		gate_base = devm_ioremap_resource(&pdev->dev, res);  in lan966x_clk_probe()
294 		hw_data->num = data->num_total_clks;  in lan966x_clk_probe()
305 	{ .compatible = "microchip,lan966x-gck", .data = &lan966x_desc },
306 	{ .compatible = "microchip,lan9691-gck", .data = &lan969x_desc },
314 		.name = "lan966x-clk",
321 MODULE_DESCRIPTION("LAN966X clock driver");