Lines Matching full:flags
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
69 unsigned long flags) in _get_maxdiv() argument
71 if (flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
73 if (flags & CLK_DIVIDER_POWER_OF_TWO) in _get_maxdiv()
75 if (flags & CLK_DIVIDER_EVEN_INTEGERS) in _get_maxdiv()
94 unsigned int val, unsigned long flags, u8 width) in _get_div() argument
96 if (flags & CLK_DIVIDER_ONE_BASED) in _get_div()
98 if (flags & CLK_DIVIDER_POWER_OF_TWO) in _get_div()
100 if (flags & CLK_DIVIDER_MAX_AT_ZERO) in _get_div()
102 if (flags & CLK_DIVIDER_EVEN_INTEGERS) in _get_div()
121 unsigned int div, unsigned long flags, u8 width) in _get_val() argument
123 if (flags & CLK_DIVIDER_ONE_BASED) in _get_val()
125 if (flags & CLK_DIVIDER_POWER_OF_TWO) in _get_val()
127 if (flags & CLK_DIVIDER_MAX_AT_ZERO) in _get_val()
129 if (flags & CLK_DIVIDER_EVEN_INTEGERS) in _get_val()
139 unsigned long flags, unsigned long width) in divider_recalc_rate() argument
143 div = _get_div(table, val, flags, width); in divider_recalc_rate()
145 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO), in divider_recalc_rate()
165 divider->flags, divider->width); in clk_divider_recalc_rate()
180 unsigned long flags) in _is_valid_div() argument
182 if (flags & CLK_DIVIDER_POWER_OF_TWO) in _is_valid_div()
227 unsigned long flags) in _div_round_up() argument
231 if (flags & CLK_DIVIDER_POWER_OF_TWO) in _div_round_up()
241 unsigned long flags) in _div_round_closest() argument
249 if (flags & CLK_DIVIDER_POWER_OF_TWO) { in _div_round_closest()
265 unsigned long flags) in _div_round() argument
267 if (flags & CLK_DIVIDER_ROUND_CLOSEST) in _div_round()
268 return _div_round_closest(table, parent_rate, rate, flags); in _div_round()
270 return _div_round_up(table, parent_rate, rate, flags); in _div_round()
274 unsigned long best, unsigned long flags) in _is_best_div() argument
276 if (flags & CLK_DIVIDER_ROUND_CLOSEST) in _is_best_div()
283 unsigned long flags) in _next_div() argument
287 if (flags & CLK_DIVIDER_POWER_OF_TWO) in _next_div()
299 unsigned long flags) in clk_divider_bestdiv() argument
308 maxdiv = _get_maxdiv(table, width, flags); in clk_divider_bestdiv()
312 bestdiv = _div_round(table, parent_rate, rate, flags); in clk_divider_bestdiv()
324 for (i = _next_div(table, 0, flags); i <= maxdiv; in clk_divider_bestdiv()
325 i = _next_div(table, i, flags)) { in clk_divider_bestdiv()
337 if (_is_best_div(rate, now, best, flags)) { in clk_divider_bestdiv()
345 bestdiv = _get_maxdiv(table, width, flags); in clk_divider_bestdiv()
354 unsigned long flags) in divider_determine_rate() argument
359 &req->best_parent_rate, table, width, flags); in divider_determine_rate()
369 unsigned long flags, unsigned int val) in divider_ro_determine_rate() argument
373 div = _get_div(table, val, flags, width); in divider_ro_determine_rate()
393 u8 width, unsigned long flags) in divider_round_rate_parent() argument
402 ret = divider_determine_rate(hw, &req, table, width, flags); in divider_round_rate_parent()
415 unsigned long flags, unsigned int val) in divider_ro_round_rate_parent() argument
424 ret = divider_ro_determine_rate(hw, &req, table, width, flags, val); in divider_ro_round_rate_parent()
440 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in clk_divider_round_rate()
447 divider->width, divider->flags, in clk_divider_round_rate()
452 divider->width, divider->flags); in clk_divider_round_rate()
461 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in clk_divider_determine_rate()
469 divider->flags, val); in clk_divider_determine_rate()
473 divider->flags); in clk_divider_determine_rate()
478 unsigned long flags) in divider_get_val() argument
484 if (!_is_valid_div(table, div, flags)) in divider_get_val()
487 value = _get_val(table, div, flags, width); in divider_get_val()
498 unsigned long flags = 0; in clk_divider_set_rate() local
502 divider->width, divider->flags); in clk_divider_set_rate()
507 spin_lock_irqsave(divider->lock, flags); in clk_divider_set_rate()
511 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_divider_set_rate()
521 spin_unlock_irqrestore(divider->lock, flags); in clk_divider_set_rate()
546 const struct clk_parent_data *parent_data, unsigned long flags, in __clk_hw_register_divider() argument
573 init.flags = flags; in __clk_hw_register_divider()
586 div->flags = clk_divider_flags; in __clk_hw_register_divider()
609 * @flags: framework-specific flags
613 * @clk_divider_flags: divider-specific flags for this clock
618 const char *parent_name, unsigned long flags, in clk_register_divider_table() argument
626 NULL, flags, reg, shift, width, clk_divider_flags, in clk_register_divider_table()
673 const struct clk_parent_data *parent_data, unsigned long flags, in __devm_clk_hw_register_divider() argument
685 parent_data, flags, reg, shift, width, in __devm_clk_hw_register_divider()