7  * Adjustable divider clock implementation
20  * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider)  in clk_div_readl()  argument
31 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_readl()
32 		return ioread32be(divider->reg);  in clk_div_readl()
34 	return readl(divider->reg);  in clk_div_readl()
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val)  in clk_div_writel()  argument
39 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_writel()
40 		iowrite32be(val, divider->reg);  in clk_div_writel()
42 		writel(val, divider->reg);  in clk_div_writel()
158 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_recalc_rate()  local
161 	val = clk_div_readl(divider) >> divider->shift;  in clk_divider_recalc_rate()
162 	val &= clk_div_mask(divider->width);  in clk_divider_recalc_rate()
164 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_divider_recalc_rate()
165 				   divider->flags, divider->width);  in clk_divider_recalc_rate()
319 	 * The maximum divider we can use without overflowing  in clk_divider_bestdiv()
330 			 * parent rate, so return the divider immediately.  in clk_divider_bestdiv()
437 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_round_rate()  local
440 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_round_rate()
443 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_round_rate()
444 		val &= clk_div_mask(divider->width);  in clk_divider_round_rate()
446 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
447 					     divider->width, divider->flags,  in clk_divider_round_rate()
451 	return divider_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
452 				  divider->width, divider->flags);  in clk_divider_round_rate()
458 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_determine_rate()  local
461 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_determine_rate()
464 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_determine_rate()
465 		val &= clk_div_mask(divider->width);  in clk_divider_determine_rate()
467 		return divider_ro_determine_rate(hw, req, divider->table,  in clk_divider_determine_rate()
468 						 divider->width,  in clk_divider_determine_rate()
469 						 divider->flags, val);  in clk_divider_determine_rate()
472 	return divider_determine_rate(hw, req, divider->table, divider->width,  in clk_divider_determine_rate()
473 				      divider->flags);  in clk_divider_determine_rate()
496 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_set_rate()  local
501 	value = divider_get_val(rate, parent_rate, divider->table,  in clk_divider_set_rate()
502 				divider->width, divider->flags);  in clk_divider_set_rate()
506 	if (divider->lock)  in clk_divider_set_rate()
507 		spin_lock_irqsave(divider->lock, flags);  in clk_divider_set_rate()
509 		__acquire(divider->lock);  in clk_divider_set_rate()
511 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in clk_divider_set_rate()
512 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in clk_divider_set_rate()
514 		val = clk_div_readl(divider);  in clk_divider_set_rate()
515 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in clk_divider_set_rate()
517 	val |= (u32)value << divider->shift;  in clk_divider_set_rate()
518 	clk_div_writel(divider, val);  in clk_divider_set_rate()
520 	if (divider->lock)  in clk_divider_set_rate()
521 		spin_unlock_irqrestore(divider->lock, flags);  in clk_divider_set_rate()
523 		__release(divider->lock);  in clk_divider_set_rate()
558 			pr_warn("divider value exceeds LOWORD field\n");  in __clk_hw_register_divider()
563 	/* allocate the divider */  in __clk_hw_register_divider()
604  * clk_register_divider_table - register a table based divider clock with
610  * @reg: register address to adjust divider
613  * @clk_divider_flags: divider-specific flags for this clock
614  * @table: array of divider/value pairs ending with a div set to 0
651  * clk_hw_unregister_divider - unregister a clk divider