1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]>
10 #include <linux/clk-provider.h>
11 #include <linux/device.h>
23  * prepare - clk_prepare only ensures that parents are prepared
24  * enable - clk_enable only ensures that parents are enabled
25  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
26  * parent - fixed parent.  No clk_set_parent support
31 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_readl()
32 		return ioread32be(divider->reg);  in clk_div_readl()
34 	return readl(divider->reg);  in clk_div_readl()
39 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_writel()
40 		iowrite32be(val, divider->reg);  in clk_div_writel()
42 		writel(val, divider->reg);  in clk_div_writel()
46 				      u8 width)  in _get_table_maxdiv()  argument
48 	unsigned int maxdiv = 0, mask = clk_div_mask(width);  in _get_table_maxdiv()
51 	for (clkt = table; clkt->div; clkt++)  in _get_table_maxdiv()
52 		if (clkt->div > maxdiv && clkt->val <= mask)  in _get_table_maxdiv()
53 			maxdiv = clkt->div;  in _get_table_maxdiv()
62 	for (clkt = table; clkt->div; clkt++)  in _get_table_mindiv()
63 		if (clkt->div < mindiv)  in _get_table_mindiv()
64 			mindiv = clkt->div;  in _get_table_mindiv()
68 static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,  in _get_maxdiv()  argument
72 		return clk_div_mask(width);  in _get_maxdiv()
74 		return 1 << clk_div_mask(width);  in _get_maxdiv()
76 		return 2 * (clk_div_mask(width) + 1);  in _get_maxdiv()
78 		return _get_table_maxdiv(table, width);  in _get_maxdiv()
79 	return clk_div_mask(width) + 1;  in _get_maxdiv()
87 	for (clkt = table; clkt->div; clkt++)  in _get_table_div()
88 		if (clkt->val == val)  in _get_table_div()
89 			return clkt->div;  in _get_table_div()
94 			     unsigned int val, unsigned long flags, u8 width)  in _get_div()  argument
101 		return val ? val : clk_div_mask(width) + 1;  in _get_div()
114 	for (clkt = table; clkt->div; clkt++)  in _get_table_val()
115 		if (clkt->div == div)  in _get_table_val()
116 			return clkt->val;  in _get_table_val()
121 			     unsigned int div, unsigned long flags, u8 width)  in _get_val()  argument
128 		return (div == clk_div_mask(width) + 1) ? 0 : div;  in _get_val()
130 		return (div >> 1) - 1;  in _get_val()
133 	return div - 1;  in _get_val()
139 				  unsigned long flags, unsigned long width)  in divider_recalc_rate()  argument
143 	div = _get_div(table, val, flags, width);  in divider_recalc_rate()
161 	val = clk_div_readl(divider) >> divider->shift;  in clk_divider_recalc_rate()
162 	val &= clk_div_mask(divider->width);  in clk_divider_recalc_rate()
164 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_divider_recalc_rate()
165 				   divider->flags, divider->width);  in clk_divider_recalc_rate()
173 	for (clkt = table; clkt->div; clkt++)  in _is_valid_table_div()
174 		if (clkt->div == div)  in _is_valid_table_div()
194 	for (clkt = table; clkt->div; clkt++) {  in _round_up_table()
195 		if (clkt->div == div)  in _round_up_table()
196 			return clkt->div;  in _round_up_table()
197 		else if (clkt->div < div)  in _round_up_table()
200 		if ((clkt->div - div) < (up - div))  in _round_up_table()
201 			up = clkt->div;  in _round_up_table()
212 	for (clkt = table; clkt->div; clkt++) {  in _round_down_table()
213 		if (clkt->div == div)  in _round_down_table()
214 			return clkt->div;  in _round_down_table()
215 		else if (clkt->div > div)  in _round_down_table()
218 		if ((div - clkt->div) < (div - down))  in _round_down_table()
219 			down = clkt->div;  in _round_down_table()
260 	return (rate - up_rate) <= (down_rate - rate) ? up : down;  in _div_round_closest()
277 		return abs(rate - now) < abs(rate - best);  in _is_best_div()
298 			       const struct clk_div_table *table, u8 width,  in clk_divider_bestdiv()  argument
308 	maxdiv = _get_maxdiv(table, width, flags);  in clk_divider_bestdiv()
345 		bestdiv = _get_maxdiv(table, width, flags);  in clk_divider_bestdiv()
353 			   const struct clk_div_table *table, u8 width,  in divider_determine_rate()  argument
358 	div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate,  in divider_determine_rate()
359 				  &req->best_parent_rate, table, width, flags);  in divider_determine_rate()
361 	req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);  in divider_determine_rate()
368 			      const struct clk_div_table *table, u8 width,  in divider_ro_determine_rate()  argument
373 	div = _get_div(table, val, flags, width);  in divider_ro_determine_rate()
375 	/* Even a read-only clock can propagate a rate change */  in divider_ro_determine_rate()
377 		if (!req->best_parent_hw)  in divider_ro_determine_rate()
378 			return -EINVAL;  in divider_ro_determine_rate()
380 		req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,  in divider_ro_determine_rate()
381 							  req->rate * div);  in divider_ro_determine_rate()
384 	req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);  in divider_ro_determine_rate()
393 			       u8 width, unsigned long flags)  in divider_round_rate_parent()  argument
402 	ret = divider_determine_rate(hw, &req, table, width, flags);  in divider_round_rate_parent()
414 				  const struct clk_div_table *table, u8 width,  in divider_ro_round_rate_parent()  argument
424 	ret = divider_ro_determine_rate(hw, &req, table, width, flags, val);  in divider_ro_round_rate_parent()
440 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_round_rate()
443 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_round_rate()
444 		val &= clk_div_mask(divider->width);  in clk_divider_round_rate()
446 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
447 					     divider->width, divider->flags,  in clk_divider_round_rate()
451 	return divider_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
452 				  divider->width, divider->flags);  in clk_divider_round_rate()
461 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_determine_rate()
464 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_determine_rate()
465 		val &= clk_div_mask(divider->width);  in clk_divider_determine_rate()
467 		return divider_ro_determine_rate(hw, req, divider->table,  in clk_divider_determine_rate()
468 						 divider->width,  in clk_divider_determine_rate()
469 						 divider->flags, val);  in clk_divider_determine_rate()
472 	return divider_determine_rate(hw, req, divider->table, divider->width,  in clk_divider_determine_rate()
473 				      divider->flags);  in clk_divider_determine_rate()
477 		    const struct clk_div_table *table, u8 width,  in divider_get_val()  argument
485 		return -EINVAL;  in divider_get_val()
487 	value = _get_val(table, div, flags, width);  in divider_get_val()
489 	return min_t(unsigned int, value, clk_div_mask(width));  in divider_get_val()
501 	value = divider_get_val(rate, parent_rate, divider->table,  in clk_divider_set_rate()
502 				divider->width, divider->flags);  in clk_divider_set_rate()
506 	if (divider->lock)  in clk_divider_set_rate()
507 		spin_lock_irqsave(divider->lock, flags);  in clk_divider_set_rate()
509 		__acquire(divider->lock);  in clk_divider_set_rate()
511 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in clk_divider_set_rate()
512 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in clk_divider_set_rate()
515 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in clk_divider_set_rate()
517 	val |= (u32)value << divider->shift;  in clk_divider_set_rate()
520 	if (divider->lock)  in clk_divider_set_rate()
521 		spin_unlock_irqrestore(divider->lock, flags);  in clk_divider_set_rate()
523 		__release(divider->lock);  in clk_divider_set_rate()
543 struct clk_hw *__clk_hw_register_divider(struct device *dev,  in __clk_hw_register_divider()
547 		void __iomem *reg, u8 shift, u8 width,  in __clk_hw_register_divider()  argument
557 		if (width + shift > 16) {  in __clk_hw_register_divider()
559 			return ERR_PTR(-EINVAL);  in __clk_hw_register_divider()
566 		return ERR_PTR(-ENOMEM);  in __clk_hw_register_divider()
583 	div->reg = reg;  in __clk_hw_register_divider()
584 	div->shift = shift;  in __clk_hw_register_divider()
585 	div->width = width;  in __clk_hw_register_divider()
586 	div->flags = clk_divider_flags;  in __clk_hw_register_divider()
587 	div->lock = lock;  in __clk_hw_register_divider()
588 	div->hw.init = &init;  in __clk_hw_register_divider()
589 	div->table = table;  in __clk_hw_register_divider()
592 	hw = &div->hw;  in __clk_hw_register_divider()
604  * clk_register_divider_table - register a table based divider clock with
606  * @dev: device registering this clock
609  * @flags: framework-specific flags
612  * @width: width of the bitfield
613  * @clk_divider_flags: divider-specific flags for this clock
617 struct clk *clk_register_divider_table(struct device *dev, const char *name,  in clk_register_divider_table()
619 		void __iomem *reg, u8 shift, u8 width,  in clk_register_divider_table()  argument
626 			NULL, flags, reg, shift, width, clk_divider_flags,  in clk_register_divider_table()
630 	return hw->clk;  in clk_register_divider_table()
651  * clk_hw_unregister_divider - unregister a clk divider
652  * @hw: hardware-specific clock data to unregister
665 static void devm_clk_hw_release_divider(struct device *dev, void *res)  in devm_clk_hw_release_divider()
670 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,  in __devm_clk_hw_register_divider()
674 		void __iomem *reg, u8 shift, u8 width,  in __devm_clk_hw_register_divider()  argument
682 		return ERR_PTR(-ENOMEM);  in __devm_clk_hw_register_divider()
685 				       parent_data, flags, reg, shift, width,  in __devm_clk_hw_register_divider()