1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
37 	.aon = AON_VAL(0x0, 5, 1, 0),
38 	.reset = RESET_VAL(0x0, 12, 11),
39 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
40 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
41 	.ndiv_int = REG_VAL(0x10, 20, 10),
42 	.ndiv_frac = REG_VAL(0x10, 0, 20),
43 	.pdiv = REG_VAL(0x14, 0, 4),
44 	.status = REG_VAL(0x30, 12, 1),
51 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
52 		.mdiv = REG_VAL(0x18, 0, 9),
57 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
58 		.mdiv = REG_VAL(0x18, 10, 9),
63 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
64 		.mdiv = REG_VAL(0x18, 20, 9),
69 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
70 		.mdiv = REG_VAL(0x1c, 0, 9),
75 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
76 		.mdiv = REG_VAL(0x1c, 10, 9),
81 		.enable = ENABLE_VAL(0x4, 11, 5, 17),
82 		.mdiv = REG_VAL(0x1c, 20, 9),
88 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll0_clk_init()
89 			    &sr_genpll0, NULL, 0, sr_genpll0_clk,  in sr_genpll0_clk_init()
91 	return 0;  in sr_genpll0_clk_init()
97 	.aon = AON_VAL(0x0, 1, 13, 12),
98 	.reset = RESET_VAL(0x0, 12, 11),
99 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
100 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
101 	.ndiv_int = REG_VAL(0x10, 20, 10),
102 	.ndiv_frac = REG_VAL(0x10, 0, 20),
103 	.pdiv = REG_VAL(0x14, 0, 4),
104 	.status = REG_VAL(0x30, 12, 1),
111 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
112 		.mdiv = REG_VAL(0x18, 0, 9),
117 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
118 		.mdiv = REG_VAL(0x18, 10, 9),
123 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
124 		.mdiv = REG_VAL(0x18, 20, 9),
129 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
130 		.mdiv = REG_VAL(0x1c, 0, 9),
135 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
136 		.mdiv = REG_VAL(0x1c, 10, 9),
140 		.enable = ENABLE_VAL(0x4, 11, 5, 17),
141 		.mdiv = REG_VAL(0x1c, 20, 9),
147 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll2_clk_init()
148 			    &sr_genpll2, NULL, 0, sr_genpll2_clk,  in sr_genpll2_clk_init()
150 	return 0;  in sr_genpll2_clk_init()
156 	.aon = AON_VAL(0x0, 1, 19, 18),
157 	.reset = RESET_VAL(0x0, 12, 11),
158 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
159 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
160 	.ndiv_int = REG_VAL(0x10, 20, 10),
161 	.ndiv_frac = REG_VAL(0x10, 0, 20),
162 	.pdiv = REG_VAL(0x14, 0, 4),
163 	.status = REG_VAL(0x30, 12, 1),
170 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
171 		.mdiv = REG_VAL(0x18, 0, 9),
176 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
177 		.mdiv = REG_VAL(0x18, 10, 9),
183 	iproc_pll_clk_setup(node, &sr_genpll3, NULL, 0, sr_genpll3_clk,  in sr_genpll3_clk_init()
186 CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
191 	.aon = AON_VAL(0x0, 1, 25, 24),
192 	.reset = RESET_VAL(0x0, 12, 11),
193 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
194 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
195 	.ndiv_int = REG_VAL(0x10, 20, 10),
196 	.ndiv_frac = REG_VAL(0x10, 0, 20),
197 	.pdiv = REG_VAL(0x14, 0, 4),
198 	.status = REG_VAL(0x30, 12, 1),
205 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
206 		.mdiv = REG_VAL(0x18, 0, 9),
211 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
212 		.mdiv = REG_VAL(0x18, 10, 9),
217 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
218 		.mdiv = REG_VAL(0x18, 20, 9),
223 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
224 		.mdiv = REG_VAL(0x1c, 0, 9),
229 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
230 		.mdiv = REG_VAL(0x1c, 10, 9),
236 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll4_clk_init()
237 			    &sr_genpll4, NULL, 0, sr_genpll4_clk,  in sr_genpll4_clk_init()
239 	return 0;  in sr_genpll4_clk_init()
245 	.aon = AON_VAL(0x0, 1, 1, 0),
246 	.reset = RESET_VAL(0x0, 12, 11),
247 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
248 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
249 	.ndiv_int = REG_VAL(0x10, 20, 10),
250 	.ndiv_frac = REG_VAL(0x10, 0, 20),
251 	.pdiv = REG_VAL(0x14, 0, 4),
252 	.status = REG_VAL(0x30, 12, 1),
258 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
259 		.mdiv = REG_VAL(0x18, 0, 9),
263 		.enable = ENABLE_VAL(0x4, 7, 1, 12),
264 		.mdiv = REG_VAL(0x18, 10, 9),
268 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
269 		.mdiv = REG_VAL(0x18, 20, 9),
275 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll5_clk_init()
276 			    &sr_genpll5, NULL, 0, sr_genpll5_clk,  in sr_genpll5_clk_init()
278 	return 0;  in sr_genpll5_clk_init()
283 	.aon = AON_VAL(0x0, 2, 19, 18),
284 	.reset = RESET_VAL(0x0, 31, 30),
285 	.sw_ctrl = SW_CTRL_VAL(0x4, 31),
286 	.ndiv_int = REG_VAL(0x4, 16, 10),
287 	.pdiv = REG_VAL(0x4, 26, 4),
288 	.status = REG_VAL(0x38, 12, 1),
295 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
296 		.mdiv = REG_VAL(0x14, 0, 9),
301 		.enable = ENABLE_VAL(0x0, 8, 2, 14),
302 		.mdiv = REG_VAL(0x14, 10, 9),
307 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
308 		.mdiv = REG_VAL(0x14, 20, 9),
313 		.enable = ENABLE_VAL(0x0, 10, 4, 16),
314 		.mdiv = REG_VAL(0x18, 0, 9),
320 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll0_clk_init()
321 			    &sr_lcpll0, NULL, 0, sr_lcpll0_clk,  in sr_lcpll0_clk_init()
323 	return 0;  in sr_lcpll0_clk_init()
328 	.aon = AON_VAL(0x0, 2, 22, 21),
329 	.reset = RESET_VAL(0x0, 31, 30),
330 	.sw_ctrl = SW_CTRL_VAL(0x4, 31),
331 	.ndiv_int = REG_VAL(0x4, 16, 10),
332 	.pdiv = REG_VAL(0x4, 26, 4),
333 	.status = REG_VAL(0x38, 12, 1),
340 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
341 		.mdiv = REG_VAL(0x14, 0, 9),
346 		.enable = ENABLE_VAL(0x0, 8, 2, 14),
347 		.mdiv = REG_VAL(0x14, 10, 9),
352 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
353 		.mdiv = REG_VAL(0x14, 20, 9),
359 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll1_clk_init()
360 			    &sr_lcpll1, NULL, 0, sr_lcpll1_clk,  in sr_lcpll1_clk_init()
362 	return 0;  in sr_lcpll1_clk_init()
367 	.aon = AON_VAL(0x0, 2, 25, 24),
368 	.reset = RESET_VAL(0x0, 31, 30),
369 	.sw_ctrl = SW_CTRL_VAL(0x4, 31),
370 	.ndiv_int = REG_VAL(0x4, 16, 10),
371 	.pdiv = REG_VAL(0x4, 26, 4),
372 	.status = REG_VAL(0x38, 12, 1),
379 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
380 		.mdiv = REG_VAL(0x14, 0, 9),
386 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll_pcie_clk_init()
387 			    &sr_lcpll_pcie, NULL, 0, sr_lcpll_pcie_clk,  in sr_lcpll_pcie_clk_init()
389 	return 0;  in sr_lcpll_pcie_clk_init()
393 	{ .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
394 	{ .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
395 	{ .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
396 	{ .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
397 	{ .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
398 	{ .compatible = "brcm,sr-lcpll1", .data = sr_lcpll1_clk_init },
399 	{ .compatible = "brcm,sr-lcpll-pcie", .data = sr_lcpll_pcie_clk_init },
407 	probe_func = of_device_get_match_data(&pdev->dev);  in sr_clk_probe()
409 		return -ENODEV;  in sr_clk_probe()
416 		.name = "sr-clk",