Lines Matching +full:platform +full:- +full:pll
1 # SPDX-License-Identifier: GPL-2.0
17 by platform/architecture code. This method is deprecated. Modern
46 bool "PLL Driver for HSDK platform"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
202 Given a target output frequency, the driver will set the PLL and
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
230 bool "Clock driver for the Mobileye EyeQ platform"
237 provides read-only PLLs, derived from the main crystal clock (which
267 platform, also known as SL3516 or CS3516.
296 clock. These multi-function devices have two (S2MPS14) or three
297 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
321 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
338 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
339 features of the PLL are currently supported by the driver. By default,
340 configured bypass mode with this PLL.
347 Support for the APM X-Gene SoC reference, PLL, and device clocks.
365 bool "Clock driver for Loongson-2 SoC"
368 This driver provides support for clock controller on Loongson-2 SoC.
371 Say Y here to support Loongson-2 SoC clock driver.
400 tristate "Clock driver for Renesas 9-series PCIe clock generators"
405 This driver supports the Renesas 9-series PCIe clock generator
484 Support for the Canaan Kendryte K210 RISC-V SoC clocks.
493 Not all features of the PLL are currently supported
498 source "drivers/clk/baikal-t1/Kconfig"
523 source "drivers/clk/sunxi-ng/Kconfig"
564 Kunit test for the clk-fractional-divider type.