Lines Matching +full:bypass +full:- +full:attenuator +full:- +full:in

1 # SPDX-License-Identifier: GPL-2.0
16 Select this option when the clock API in <linux/clk.h> is implemented
30 implementation of the clock API in include/linux/clk.h.
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
128 by the driver, in particular it only supports XTAL input. The chip can
129 be pre-programmed to support other configurations and features not yet
130 implemented in the driver.
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
236 SoCs. Controllers live in shared register regions called OLB. Driver
237 provides read-only PLLs, derived from the main crystal clock (which
296 clock. These multi-function devices have two (S2MPS14) or three
297 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
321 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
322 FPGAs. It is commonly used in Analog Devices' reference designs.
340 configured bypass mode with this PLL.
347 Support for the APM X-Gene SoC reference, PLL, and device clocks.
365 bool "Clock driver for Loongson-2 SoC"
368 This driver provides support for clock controller on Loongson-2 SoC.
371 Say Y here to support Loongson-2 SoC clock driver.
400 tristate "Clock driver for Renesas 9-series PCIe clock generators"
405 This driver supports the Renesas 9-series PCIe clock generator
442 and jitter attenuator ICs with fractional and integer dividers.
484 Support for the Canaan Kendryte K210 RISC-V SoC clocks.
498 source "drivers/clk/baikal-t1/Kconfig"
523 source "drivers/clk/sunxi-ng/Kconfig"
564 Kunit test for the clk-fractional-divider type.