1 // SPDX-License-Identifier: GPL-2.0-only
26  * CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit.
28 #define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1)
29 #define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3)
30 #define EBI2_CS2_ENABLE_MASK BIT(4)
31 #define EBI2_CS3_ENABLE_MASK BIT(5)
32 #define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7)
33 #define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9)
41  * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42  *             memory continues to drive the data bus after OE is de-asserted.
45  * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49  * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51  * Bits 15-8:  RD_DELTA initial latency for read cycles inserted for the first
53  * Bits 7-4:   WR_WAIT number of wait cycles for every write access, 0=1 cycle
55  * Bits 3-0:   RD_WAIT number of wait cycles for every read access, 0=1 cycle
74  * Bits 31-28: ?
75  * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
78  * Bits 18-24: ?
79  * Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE
86  * We have not been able to figure out which bit fields these correspond to
89  * device enable" flag somewhere for 8bit memories.
103  * struct cs_data - struct with info on a chipselect setting
154  * struct ebi2_xmem_prop - describes an XMEM config property
159  * @shift: the bit field start in the SLOW or FAST register for this
166 	u16 shift;  member
171 		.prop = "qcom,xmem-recovery-cycles",
174 		.shift = EBI2_XMEM_RECOVERY_SHIFT,
177 		.prop = "qcom,xmem-write-hold-cycles",
180 		.shift = EBI2_XMEM_WR_HOLD_SHIFT,
183 		.prop = "qcom,xmem-write-delta-cycles",
186 		.shift = EBI2_XMEM_WR_DELTA_SHIFT,
189 		.prop = "qcom,xmem-read-delta-cycles",
192 		.shift = EBI2_XMEM_RD_DELTA_SHIFT,
195 		.prop = "qcom,xmem-write-wait-cycles",
198 		.shift = EBI2_XMEM_WR_WAIT_SHIFT,
201 		.prop = "qcom,xmem-read-wait-cycles",
204 		.shift = EBI2_XMEM_RD_WAIT_SHIFT,
207 		.prop = "qcom,xmem-address-hold-enable",
210 		.shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT,
213 		.prop = "qcom,xmem-adv-to-oe-recovery-cycles",
216 		.shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT,
219 		.prop = "qcom,xmem-read-hold-cycles",
222 		.shift = EBI2_XMEM_RD_HOLD_SHIFT,
240 	val |= csd->enable_mask;  in qcom_ebi2_setup_chipselect()
252 		ret = of_property_read_u32(np, xp->prop, &val);  in qcom_ebi2_setup_chipselect()
255 				xp->prop, csindex);  in qcom_ebi2_setup_chipselect()
260 		if (xp->max == 1 && val) {  in qcom_ebi2_setup_chipselect()
261 			if (xp->slowreg)  in qcom_ebi2_setup_chipselect()
262 				slowcfg |= BIT(xp->shift);  in qcom_ebi2_setup_chipselect()
264 				fastcfg |= BIT(xp->shift);  in qcom_ebi2_setup_chipselect()
265 			dev_dbg(dev, "set %s flag\n", xp->prop);  in qcom_ebi2_setup_chipselect()
270 		if (val > xp->max) {  in qcom_ebi2_setup_chipselect()
273 				xp->prop, val, xp->max);  in qcom_ebi2_setup_chipselect()
274 			val = xp->max;  in qcom_ebi2_setup_chipselect()
276 		if (xp->slowreg)  in qcom_ebi2_setup_chipselect()
277 			slowcfg |= (val << xp->shift);  in qcom_ebi2_setup_chipselect()
279 			fastcfg |= (val << xp->shift);  in qcom_ebi2_setup_chipselect()
280 		dev_dbg(dev, "set %s to %u\n", xp->prop, val);  in qcom_ebi2_setup_chipselect()
287 		writel(slowcfg, ebi2_xmem + csd->slow_cfg);  in qcom_ebi2_setup_chipselect()
289 		writel(fastcfg, ebi2_xmem + csd->fast_cfg);  in qcom_ebi2_setup_chipselect()
294 	struct device_node *np = pdev->dev.of_node;  in qcom_ebi2_probe()
296 	struct device *dev = &pdev->dev;  in qcom_ebi2_probe()
363 				"invalid chipselect %u, we only support 0-5\n",  in qcom_ebi2_probe()
391 	{ .compatible = "qcom,msm8660-ebi2", },
392 	{ .compatible = "qcom,apq8060-ebi2", },
399 		.name = "qcom-ebi2",