Lines Matching +full:loss +full:- +full:of +full:- +full:signal
10 of the GNU General Public License (GPL), incorporated herein by reference.
15 WITHOUT ANY WARRANTY; without even the implied warranty of
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
23 in terms of PHY type, the size of control memory and the size of
29 Complete the ABR logic of the driver, and added the ABR work-
32 Add the flow control logic to the driver to allow rate-limit VC.
34 Add the support of all the variants of the Interphase ATM PCI
127 #define ATM_DESC(skb) (skb->protocol)
128 #define IA_SKB_STATE(skb) (skb->protocol)
157 #define NR_VCI 1024 /* number of VCIs */
159 #define NR_VCI_4K 4096 /* number of VCIs */
177 #define NRMCODE 5 /* 0 - 7 */
178 #define TRMCODE 3 /* 0 - 7 */
180 #define ATDFCODE 2 /* 0 - 15 */
182 /*---------------------- Packet/Cell Memory ------------------------*/
183 #define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
185 #define DFL_TX_BUFFERS 50 /* number of packet buffers for Tx
186 - descriptor 0 unused */
188 #define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
190 #define DFL_RX_BUFFERS 50 /* number of packet buffers for Rx
191 - descriptor 0 unused */
245 u_short remainder; /* ABR and UBR fields - last 10 bits*/
258 #define CRC_APPEND 0x40 /* for status field - CRC-32 append */
329 /*--------SAR stuff ---------------------*/
335 /*------------ PCI Memory Space Map, 128K SAR memory ----------------*/
337 #define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
345 /*------------ Bus interface control registers -----------------*/
350 #define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
394 /*--------------- Segmentation control registers -----------------*/
479 /*----------------- Reassembly control registers ---------------------*/
555 /*----------------- Front End registers/ DMA control --------------*/
556 /* There is a lot of documentation error regarding these offsets ???
557 eg:- 2 offsets given 800, a00 for rx counter
562 #define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
563 #define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
564 #define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
565 #define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
567 /*--------------------------- RAM ---------------------------*/
582 #define TX_DESC_TABLE_SZ 128 /* Number of entries in the Transmit
610 #define RX_DESC_TABLE_SZ 736 /* Number of entries in the Receive
612 #define VP_TABLE_SZ 256 /* Number of entries in VPTable */
613 #define RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */
614 #define REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */
631 /*-------------------- Base Registers --------------------*/
648 u_int filler5[0x17 - 0x06];
650 u_int filler18[0x20 - 0x18];
661 u_int filler2a[0x2C - 0x2A];
665 u_int filler2f[0x30 - 0x2F];
674 u_int filler38[0x40 - 0x38];
676 ffreg_t desc_base; /* Base address of descriptor table */
677 u_int filler42[0x45 - 0x42];
685 u_int filler4c[0x58 - 0x4c];
689 u_int filler5b[0x5d - 0x5b];
691 u_int filler5e[0x6a - 0x5e];
708 u_int filler7a[0x7c-0x7a];
709 ffreg_t out_rate_head; /* Out of rate head */
710 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
713 u_int fillercc[0x100-0xcc]; /* pad out to full address space */
723 u_int filler6[0x08 - 0x06];
725 u_int filler2[0x0c - 0x09];
728 u_int filler3[0x0f - 0x0e];
734 u_int filler14[0x16 - 0x14];
736 rreg_t tmout_range; /* Range of reassembley IDs for timeout */
738 rreg_t tmout_indx; /* index of pkt being tested for aging */
739 u_int filler1a[0x1c - 0x1a];
742 rreg_t abr_lkup_base; /* Base address of ABR VC Table */
743 u_int filler1f[0x24 - 0x1f];
756 u_int filler30[0x34 - 0x30];
762 u_int filler39[0x42 - 0x39];
765 rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
766 u_int filler45[0x84 - 0x45];
769 u_int filler86[0x8c - 0x86];
772 u_int filler8e[0x100-0x8e]; /* pad out to full address space */
810 u32 pcr; /* Peak Cell Rate (24-bit) */
816 u32 mcr; /* Min Cell Rate (24-bit) */
817 u32 icr; /* Initial Cell Rate (24-bit) */
818 u32 tbe; /* Transient Buffer Exposure (24-bit) */
819 u32 frtt; /* Fixed Round Trip Time (24-bit) */
821 #if 0 /* Additional Parameters of TM 4.0 */
822 bits 31 30 29 28 27-25 24-22 21-19 18-9
823 -----------------------------------------------------------------------------
825 -----------------------------------------------------------------------------
828 u8 nrm; /* Max # of Cells for each forward RM
829 cell (3-bit) */
830 u8 trm; /* Time between forward RM cells (3-bit) */
831 u16 adtf; /* ACR Decrease Time Factor (10-bit) */
832 u8 cdf; /* Cutoff Decrease Factor (3-bit) */
833 u8 rif; /* Rate Increment Factor (4-bit) */
834 u8 rdf; /* Rate Decrease Factor (4-bit) */
901 SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
902 SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
909 SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
910 SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
911 SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
924 SUNI_RPOP_PATH_SIG = 0x0dc, /* RPOP Path Signal Label */
925 SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
926 SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
937 SUNI_TPOP_PATH_SIG = 0x120, /* TPOP Path Signal Lable */
962 u16 rsop_oof_state; // 1 = out of frame
963 u16 rsop_lof_state; // 1 = loss of frame
964 u16 rsop_los_state; // 1 = loss of signal
965 u32 rsop_los_count; // loss of signal count
966 u32 rsop_bse_count; // section BIP-8 error count
970 u32 rlop_lbe_count; // BIP-24 count
976 u32 rpop_bip_count; // path BIP-8 error count
978 u16 rpop_psig; // path signal label value
988 /*-----base pointers into (i)chipSAR+ address space */
1015 struct atm_vcc **rx_open; /* list of all open VCs */
1026 unsigned int pci_map_size; /*pci map size of board */
1039 unsigned int tx_dma_cnt; // number of elements on dma queue
1040 unsigned int rx_dma_cnt; // number of elements on rx dma queue
1041 unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR
1043 unsigned int rx_mark_cnt; // number of elements on mark queue
1059 #define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1060 #define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1091 #define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */
1100 #define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
1138 /* SUNI_RESERVED1 (0x13 - 0x11) */
1153 /* SUNI_RESERVED2 (0x23 - 0x21) */
1203 /* SUNI_RESERVED3 (0x57 - 0x54) */
1230 /* SUNI_PAD5 (0x7f - 0x71) */
1232 /* SUNI_PAD6 (0xff - 0x80) */
1252 #define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */
1256 #define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */
1257 #define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/
1258 #define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */
1259 #define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */
1268 #define SUNI_DS3_IDLV 0x08 /* Idle signal state */
1269 #define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/
1270 #define SUNI_DS3_OOFV 0x02 /* Out of frame state */
1271 #define SUNI_DS3_LOSV 0x01 /* Loss of signal state */
1277 #define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */
1279 #define SUNI_E3_COFAI 0x08 /* Change of frame align intr */
1280 #define SUNI_E3_OOFI 0x04 /* Out of frame intr status */
1281 #define SUNI_E3_LOS 0x02 /* Loss of signal state */
1282 #define SUNI_E3_OOF 0x01 /* Out of frame state */
1287 #define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/
1318 #define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/
1320 #define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */
1321 #define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */
1324 #define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */
1343 * a list of the commands that can be sent to the NOVRAM
1374 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1376 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1388 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1390 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1398 * Clock each of the command bits out in the correct order with SK
1409 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1447 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \